hi5728 Intersil Corporation, hi5728 Datasheet - Page 15

• Manufacturer Part Number: hi5728
• Description: 10-bit, 125/60msps, Dual High Speed Cmos D/a Converter
• Manufacturer: Intersil Corporation

Timing Diagrams
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
D9-D0
CLK
I
OUT
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM
D9-D0
I
CLK
t
OUT
PD
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
t
SETT
15
t
PD
t
SU
50%
1 LSB ERROR BAND
t
PW1
t
SETT
t
HLD
t
PW2
t
PD
t
SU
HI5728
t
from the beginning of the output transition. The
measurement was done by switching from code 0 to 256, or
quarter scale. Termination impedance was 25
parallel resistance of the output 50
50
error band without overdriving the oscilloscope.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification. This is tested under
the same conditions as ‘Output Settling Time.’
SETT
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT
t
HLD
Ω
input. This also aids the ability to resolve the specified
V
t
PD
t
METHOD
SU
WIDTH (W)
t
SETT
t
HLD
GLITCH AREA =
HEIGHT (H)
Ω
and the oscilloscope’s
1
/
2
50%
(H x W)
t(ps)
Ω
due to the