hi5728 Intersil Corporation, hi5728 Datasheet - Page 4

• Manufacturer Part Number: hi5728
• Description: 10-bit, 125/60msps, Dual High Speed Cmos D/a Converter
• Manufacturer: Intersil Corporation

Pin Descriptions
13, 18, 19, 25
10, 28, 41, 44
9, 29, 40, 45
1-6, 48-46
PIN NO.
14, 24
11, 27
12, 26
39-30
15
23
22
17
16
20
21
43
42
8
QD9 (MSB) Through
ID9 (MSB) Through
ICOMP1, QCOMP1
PIN NAME
QD0 (LSB)
ID0 (LSB)
QOUTB
QOUTA
REFLO
SLEEP
FSADJ
REFIO
IOUTB
IOUTA
AGND
DGND
AV
DV
QCLK
ICLK
NC
DD
DD
4
Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
channel.
Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
channel.
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pull-down current.
Connect to analog ground to enable internal 1.2V reference or connect to AV
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x I
Reduces noise. Connect each to AV
pins MUST be tied together externally.
Analog Ground Connections.
The complimentary current output of the I channel. Bits set to all 0s gives full scale current.
Current output of the I channel. Bits set to all 1s gives full scale current.
The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.
Current output of the Q channel. Bits set to all 1s gives full scale current.
No Connect. Recommended: connect to ground.
Analog Supply (+2.7V to +5.5V).
Digital Ground.
Supply voltage for digital circuitry (+2.7V to +5.5V).
Clock input for I channel. Positive edge of clock latches data.
Clock input for Q channel. Positive edge of clock latches data.
HI5728
FSADJ
.
DD
with 0.1µF capacitor near each pin. The ICOMP1 and QCOMP1
PIN DESCRIPTION
DD
to disable.