hi5728 Intersil Corporation, hi5728 Datasheet - Page 17

• Manufacturer Part Number: hi5728
• Description: 10-bit, 125/60msps, Dual High Speed Cmos D/a Converter
• Manufacturer: Intersil Corporation

Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ± 60 ppm /
temperature range of the converter. It is recommended that a
0.1µF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (15)
selects the reference. The internal reference can be selected if
pin 15 is tied low (ground). If an external reference is desired,
then pin 15 should be tied high (to the analog supply voltage)
and the external reference driven into REFIO, pin 23. The full
scale output current of the converter is a function of the voltage
reference used and the value of R
the 2mA to 20mA range, through operation below 2mA is
possible, with performance degradation.
If the internal reference is used, V
approximately 1.16V (pin 22). If an external reference is used,
V
I
I
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ R
resistor, then the input coding to output current will resemble
the following:
Outputs
IOUTA and IOUTB (or QOUTA and QOUTB) are
complementary current outputs. The sum of the two currents
is always equal to the full scale output current minus one
LSB. If single ended use is desired, a load resistor can be
used to convert the output current to a voltage. It is
recommended that the unused output be either grounded or
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OUT
OUT
FSADJ
INPUT CODE (D9-D0)
TABLE 1. INPUT CODING vs OUTPUT CURRENT (Per DAC)
(Full Scale) is:
(Full Scale) = (V
11111 11111
10000 00000
00000 00000
will equal the external reference. The calculation for
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FSADJ
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IOUTA (mA)
/R
17
o
SET
C drift coefficient over the full
20
10
0
SET
FSADJ
) x 32.
. I
OUT
will equal
should be within
IOUTB (mA)
SET
10
20
0
HI5728
equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of
-0.3V to 1.25V. R
output voltage is produced in conjunction with the output full
scale current, which is described above in the ‘Reference’
section. If a known line impedance is to be driven, then the
output load resistor should be chosen to match this
impedance. The output voltage equation is:
V
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 16
and 17 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mV
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
V
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. The 50Ω load on the output of the
transformer represents the spectrum analyzer’s input
impedance.
OUT
OUT
PIN 17 (20)
PIN 16 (21)
= 2 x I
= I
OUT
OUT
IOUTB (QOUTB)
IOUTA (QOUTA)
X R
LOAD
x R
LOAD
EQ ,
should be chosen so that the desired
.
FIGURE 42.
where R
100Ω
50Ω
50Ω
EQ
is ~12.5Ω .
V
OUT
= (2 x I
P-P
50Ω
amplitude
OUT
x R
EQ
)V