hi5703 Intersil Corporation, hi5703 Datasheet - Page 12

• Manufacturer Part Number: hi5703
• Description: 10-bit, 40 Msps A/d Converter
• Manufacturer: Intersil Corporation

Detailed Description
Theory of Operation
The HI5703 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction. Figure 15 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal
phase,
capacitors, C
are discharged to analog ground. At the falling edge of
the input signal is sampled on the bottom plates of the
sampling capacitors. In the next clock phase,
bottom plates of the sampling capacitors are connected
2
, derived from the master clock. During the sampling
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
1
, the input signal is applied to the sampling
S
. At the same time the holding capacitors, C
DV
DV
V
DV
NAME
DGND
DGND
DGND
AGND
V
AGND
AV
AV
TABLE 1. PIN DESCRIPTION
V
V
V
DFS
CLK
REF
REF
OE
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IN
IN
DC
CC1
CC1
CC2
CC
CC
+
-
+
-
4-12
Digital Supply (+5.0V)
Digital Ground
Digital Supply (+5.0V)
Digital Ground
Analog Supply (+5.0V)
Analog Ground
Positive Reference Voltage Input
Negative Reference Voltage Input
Positive Analog Input
Negative Analog Input
DC Bias Voltage Output
Analog Ground
Analog Supply (+5.0V)
Digital Output Enable Control Input
Data Format Select Input
Data Bit 9 Output (MSB)
Data Bit 8 Output
Data Bit 7 Output
Data Bit 6 Output
Data Bit 5 Output
Digital Ground
Sample Clock Input
Digital Output Supply (+3.3V to +5V)
Data Bit 4 Output
Data Bit 3 Output
Data Bit 2 Output
Data Bit 1 Output
Data Bit 0 Output (LSB)
DESCRIPTION
2
, the two
1
and
1
H
,
together and the holding capacitors are switched to the op-
amp output nodes. The charge then redistributes between
C
output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sample-
and-hold function but will also convert a single-ended input
to a fully-differential output for the converter core. During the
sampling phase, the V
switch and C
components result in a typical full power input bandwidth of
250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, nine identical pipeline subconverter
stages, each containing a two-bit flash converter and a two-
bit multiplying digital-to-analog converter, follow the S/H
circuit with the tenth stage being a one bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The two-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final ten bit output for the converter.
Because of the pipeline nature of this converter, the data on
the bus is output at the 7th cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse.
The output data is synchronized to the external clock by a
double buffered latching technique.
The digital output bits are available in offset binary or two’s
complement format, the format being set by the Data Format
Select (DFS) input.
S
and C
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
V
V
IN
IN
+
-
H
completing one sample-and-hold cycle. The
S
. The relatively small values of these
1
1
2
C
C
S
S
IN
1
1
pins see only the on-resistance of a
+
-
+
-
C
C
H
H
1
1
V
V
OUT+
OUT-