uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 41

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 26 Description of register bits (address 00H)
Table 27 Crystal oscillator output frequencies
2003 Apr 10
Based on 32 kHz
Based on 44.1 kHz
1 and 0 CLKOUT_SEL[1:0] Clock output select. If these bits are 00 or 10, then the BCKI and BCKO clock
12 to 8 XTL_DIV[4:0]
7 to 4
Stereo audio codec with SPDIF interface
BIT
15
14
13
XTL_DIV4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
EXPU
PON_XTALPLL
MODE[3:0]
ws_detct_EN
ws_detct_set
SYMBOL
XTL_DIV3
0
0
0
0
0
0
0
0
1
1
1
1
EXPU. Bit EXPU is reserved for manufacturers evaluation and should be kept
untouched for normal operation of UDA1355H.
reserved
Power control crystal oscillator and PLL. If this bit is logic 0, then the crystal
oscillator and PLL are turned off; if this bit is logic 1, then the crystal oscillator and PLL
are running.
Crystal oscillator clock divider setting. Value to select the sampling frequency and
the system clock output frequency (256f
BCKI and BCKO clock frequency of digital interface running with crystal oscillator clock
will be 64f
Microcontroller application mode setting. Value to select the microcontroller
application mode (see Table 28).
Word select detector enable.If this bit is logic 0, then WS detector is disabled; if this
bit is logic 1, then WS detector is enabled.
Word select detector limit setting. If this bit is logic 0, then the lower frequency limit
of the WS detector is 4095 clock cycles (3 kHz); if this bit is logic 1, then the lower
frequency limit of the WS detector is 2047 clock cycles (6 kHz).
frequency of digital interface running with FPLL clock will be 64f
48f
bits XTL_DIV[4:0]:
00 = FPLL clock 256f
01 = FPLL clock 384f
10 = crystal clock
11 = crystal clock
s
. The selection between 256f
XTL_DIV2
s
; when 384f
0
0
0
0
1
1
1
1
0
0
0
0
s
s
s
is selected, it will be 48f
XTL_DIV1
41
0
0
1
1
0
0
1
1
0
0
1
1
s
and 384f
DESCRIPTION
s
or 384f
s
XTL_DIV0
for the crystal clock output is set via the
s
s
). When 256f
0
1
0
1
0
1
0
1
0
1
0
1
(see Table 27).
256
384
256
384
256
384
256
384
256
384
256
384
s
Preliminary specification
is selected, the master
s
; otherwise, it will be
OUTPUT RATE
16 kHz
16 kHz
32 kHz
32 kHz
64 kHz
64 kHz
22.05 kHz
22.05 kHz
44.1 kHz
44.1 kHz
88.2 kHz
88.2 kHz
UDA1355H