uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 49

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 46 Register address 13H
Table 47 Description of register bits (address 13H)
Table 48 DAC gain setting
Notes
1. See Table 52.
2. X = don’t care
2003 Apr 10
Symbol
Default
Symbol
Default
Stereo audio codec with SPDIF interface
7 and 6
10 to 8
2 to 0
BIT
BIT
BIT
15
14
13
12
11
5
4
3
GS
0
1
1
1
1
-
MTM
GS
MIXGAIN
MT2
DE2_[2:0]
MTNS[1:0]
WS_SEL
DE_SW
MT1
DE1_[2:0]
SYMBOL
MTNS1
15
0
7
0
reserved
Master mute. If this bit is logic 0 then there is no master mute or the master de-mute is in
progress; if this bit is logic 1 then the master mute is in progress or muted.
Gain select. See Table 48.
Mixer gain select. See Tables 48 and 49.
Channel 2 mute. If this bit is logic 0 then channel 2 is not muted or the de-mute is in
progress; if this bit is logic 1 then channel 2 is muted or the muting is in progress.
De-emphasis setting for channel 2. See Table 50.
Interpolator mute. Selection:
WS signal select. If this bit is logic 0 then WS_DET is selected for the WS detection; if
this bit is logic 1 then FPLL is selected for the WS detection.
De-emphasis select. If this bit is logic 0 then SPDIF pre-emphasis information is
selected; if this bit is logic 1 then the de-emphasis setting is selected.
Channel 1 mute. If this bit is logic 0 then channel 1 is not muted or the de-mute is in
progress; if this bit is logic 1 then channel 1 is muted or the muting is in progress.
De-emphasis setting for channel 1. See Table 50.
MTNS0
00 = no mute
01 = if no WS signal is detected, the noise shaper of the interpolator mute
1x = the noise shaper of the interpolator mute
MTM
14
0
6
0
MIX
X
WS_SEL
0
1
0
1
(2)
(1)
GS
13
0
5
0
MIXGAIN
DE_SW
49
12
0
4
0
DESCRIPTION
MIX_GAIN
MT2
MT1
X
11
1
0
3
0
0
1
1
(2)
DE2_2
DE1_2
10
0
2
0
Preliminary specification
DAC GAIN (dB)
DE2_1
DE1_1
9
0
1
0
UDA1355H
0
6
0
6
6
DE2_0
DE1_0
8
0
0
0