uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 47

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 42 Register address 12H
Table 43 Description of register bits (address 12H)
2003 Apr 10
Symbol
Default
Symbol
Default
VC2_7
VC1_7
Stereo audio codec with SPDIF interface
15 and 14
13 and 12
11 to 8
1
1
1
1
1
1
1
1
:
:
BIT
BIT
BIT
7
VC2_6
VC1_6
0
1
1
1
1
1
1
1
:
:
M[1:0]
TRL[1:0]
BBL[3:0]
BB_OFF
SYMBOL
BB_OFF
M1
15
0
7
0
VC2_5
VC1_5
1
0
0
0
0
1
1
1
:
:
Sound feature mode. Value to program the sound processing filter sets (modes) of bass
boost and treble:
Treble settings left. Value to program the left channel treble setting. Both left and right
channels will follow the left channel setting when bit BASS_SEL = 1. The used filter set is
selected with the sound feature mode bits M1 and M2 (see Table 44).
Normal bass boost settings left. Value to program the left bass boost settings. The
used filter set is selected by the sound feature mode bits M1 and M2 (see Table 45).
Resonant bass boost. If this bit is logic 0 then the resonant bass boost is enabled; if this
bit is logic 1 then the resonant bass boost is disabled.
BB_FIX
VC2_4
VC1_4
00 = flat set
01 = minimum set
10 = minimum set
11 = maximum set
M0
14
1
0
1
1
1
0
0
1
0
6
0
:
:
VC2_3
VC1_3
1
0
0
1
1
0
0
1
:
:
TRR1
TRL1
13
0
5
0
VC2_2
VC1_2
1
0
1
0
1
0
1
1
:
:
TRR0
TRL0
47
12
0
4
0
VC2_1
VC1_1
0
0
0
0
0
0
0
0
:
:
DESCRIPTION
BBR3
VC2_0
VC1_0
BBL3
11
0
0
3
0
0
0
0
0
0
0
0
:
:
:
:
48
50
60
63
66
72
BBR2
BBL2
10
0
2
0
VOLUME (dB)
Preliminary specification
BBR1
BBL1
9
0
1
0
UDA1355H
BBR0
BBL0
8
0
0
0