pca9632 NXP Semiconductors, pca9632 Datasheet - Page 16

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pca9632

Manufacturer Part Number
pca9632
Description
Pca9632 4-bit Fm I?c-bus Low Power Led Driver
Manufacturer
NXP Semiconductors
Datasheet

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Table 15.
8. Characteristics of the I
PCA9632_1
Objective data sheet
Type of control
Individual LED brightness
without dimming
Individual LED brightness
with global dimming
Blinking (fast)
Blinking (slow)
Dimming and blinking resolution
8.1.1 START and STOP conditions
8.1 Bit transfer
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Fig 9. Bit transfer
LDRx
10
11
11
11
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
DMBLNK
X
0
1
1
2
SDA
SCL
Figure
C-bus
Rev. 01 — 28 September 2007
GRPPWM
X
16 steps
64 steps
256 steps
10.)
GRPFREQ
X
X
256 steps
256 steps
data valid
data line
stable;
Figure
allowed
change
of data
Frequency
1.5625 kHz
190 Hz with 6.25 kHz modulation
blink frequency = 6 Hz to 24 Hz
PWMx frequency = 1.5625 kHz
blink frequency = 0.09 Hz to 6 Hz
PWMx frequency = 1.5625 kHz
4-bit Fm+ I
9).
2
C-bus low power LED driver
mba607
PCA9632
© NXP B.V. 2007. All rights reserved.
PWMx
256 steps
64 steps
256 steps
256 steps
16 of 32

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