adv7344 Analog Devices, Inc., adv7344 Datasheet - Page 44

• Manufacturer Part Number: adv7344
• Description: Multiformat Video Encoder Six 14-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

ADV7344
INPUT CONFIGURATION
The ADV7344 supports a number of different input modes. The
desired input mode is selected using Subaddress 0x01, Bits[6:4].
The ADV7344 defaults to standard definition only (SD only)
upon power-up. Table 31 provides an overview of all possible
input configurations. Each input mode is described in detail in
the following sections.
STANDARD DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 000
Standard definition (SD) YCrCb data can be input in 4:2:2 format.
Standard definition (SD) RGB data can be input in 4:4:4 format.
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the S_HSYNC
and S_VSYNC pins.
8-/10-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 0
In 8-/10-bit 4:2:2 YCrCb input mode, the interleaved pixel data
is input on Pin S9 to Pin S2/S0 (or Pin Y9 to Pin Y2/Y0, depending
on Subaddress 0x01, Bit 7), with S0/Y0 being the LSB in 10-bit
input mode. ITU-R BT.601/656 input standard is supported.
16-/20-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1
Table31. Input Configuration
Input Mode
000
001
010
011
100
111
1
2
3
4
5
6
7
8
The input mode is determined by Subaddress 0x01, Bits[6:4].
In SD only (YCrCb) mode, the format of the input data is determined by Subaddress 0x88, Bits[4:3]. See Table 26 for more information.
For 8-/16-/24-bit inputs, only the eight most significant bits (MSBs) of each applicable input bus are used
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
In ED/HD-SDR only (YCrCb) mode, the format of the input data is determined by Subaddress 0x33, Bit 6. See Table 19 for more information.
ED = enhanced definition = 525p and 625p.
The bus width of the ED/HD input data is determined by Subaddress 0x33, Bit 2 (0 = 8-bit, 1 = 10-bit). See Table 19 for more information.
The bus width of the SD input data is determined by Subaddress 0x88, Bit 4 (0 = 8-bit, 1 = 10-bit). See Table 26 for more information.
SD Only
8-/10-Bit YCrCb
16-/20-Bit YCrCb
8-/10-Bit YCrCb
16-/20-Bit YCrCb
24-/30-Bit RGB
ED/HD-SDR Only
16-/20-Bit YCrCb
24-/30-Bit YCrCb
24-/30-Bit RGB
ED/HD-DDR Only
(8-/10-Bit)
SD, ED/HD-SDR
(24-/30-Bit)
SD, ED/HD-DDR
(16-/20-Bit)
ED Only (54 MHz)
(8-/10-Bit)
1
3, 6, 7
3, 6, 7
3, 6, 7, 8
3, 6, 7, 8
4
4
2, 3
2, 3, 4
2, 3
2, 3, 4
3, 5, 6, 7
9
8
7
6
YCrCb (SD)
YCrCb (SD)
5
YCrCb
Cr
S
Y
R
R
4
3
2
1
0
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9
ED/HD RGB Input Enable (0x35[1]) = 0
ED/HD RGB Input Enable (0x35[1]) = 1
8
SD RGB Input Enable (0x87[7]) = 1
Y/C/S Bus Swap (0x01[7]) = 0
Y/C/S Bus Swap (0x01[7]) = 1
7
In 16-/20-bit 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin S9 to Pin S2/S0 (or Pin Y9 to Pin Y2/Y0, depending on
Subaddress 0x01, Bit 7), with S0/Y0 being the LSB in 20-bit
input mode. The CrCb pixel data is input on Pin Y9 to Pin
Y2/Y0 (or Pin C9 to Pin C2/C0, depending on Subaddress 0x01,
Bit 7), with Y0/C0 being the LSB in 20-bit input mode.
24-/30-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
In 24-/30-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S9 to Pin S2/S0, the green pixel data is input on Pin Y9 to
Pin Y2/Y0, and the blue pixel data is input on Pin C9 to Pin C2/C0.
S0, Y0, and C0 are the respective bus LSBs in 30-bit input mode.
6
YCrCb (ED/HD)
Y (ED/HD)
5
YCrCb
YCrCb
YCrCb
CrCb
Y
Y
G
Y
Y
G
4
NOTES
1
SELECTED BY SUBADDRESS 0x01, BIT 7.
3
DECODER
MPEG2
Figure 51. SD Only Example Application
2
YCrCb
1
0
27MHz
10
2
9
8
CLKIN_A
S[9:0] OR Y[9:0]
7
S_VSYNC,
S_HSYNC
ADV7344
6
CrCb (ED/HD)
5
CrCb
CrCb
Cb
C
B
B
4
1
3
2
1
0