adv7344 Analog Devices, Inc., adv7344 Datasheet - Page 50

• Manufacturer Part Number: adv7344
• Description: Multiformat Video Encoder Six 14-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

ADV7344
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for
nonstandard input video, that is, in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
the incoming VSYNC signal.
This control is available in all slave-timing modes except Slave
Mode 0.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV7344 is able to accept input data that contains VBI
data (such as CGMS, WSS, VITS) in SD, ED, and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;
Subaddress 0x83, Bit 4 for SD), VBI data is not present at the
output and the entire VBI is blanked. These control bits are
valid in all master and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Line 13 to Line 42 of each frame, or on Line 6 to
Line 43 for the ITU-R BT.1358 (625p) standard.
VBI data can be present on Line 10 to Line 20 for NTSC and on
Line 7 to Line 22 for PAL.
RTC
1
2
3
4
5
FOR EXAMPLE, VCR OR CABLE.
F
SEQUENCE BIT
RESET ADV7344 DDS.
SELECTED BY SUBADDRESS 0x01, BIT 7.
F
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
COMPOSITE
SC
SC
Figure 62. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits[2:1] = 11)
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7344 F
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS.
VIDEO
H/L TRANSITION
COUNT START
1
TIME SLOT 01
128
ADV7403
VIDEO
DECODER
LCC1
LOW
13
SUBCARRIER
14 BITS
PHASE
P19 TO P10
SFL
14
0
4 BITS
RESERVED
21
19
Rev. 0 | Page 50 of 88
CLKIN_A
SFL/MISO
Y9 TO Y0/
S9 TO S0
SAMPLE
ADV7344
F
VALID
SC
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
If CGMS is enabled and VBI is disabled, the CGMS data is
nevertheless available at the output.
SD SUBCARRIER FREQUENCY REGISTERS
Subaddress 0x8C to Subaddress 0x8F
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using:
where the sum is rounded to the nearest integer. For example, in
NTSC mode:
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD F
SD F
SD F
SD F
Programming the F
The subcarrier frequency register value is divided into four F
registers as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte has been
received by the ADV7344.
5
PLL INCREMENT
SC
INVALID
SAMPLE
SC
SC
SC
SC
Subcarrier
Subcarrier
Number
Number
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DDS REGISTER IS
Register 0: 0x1F
Register 1: 0x7C
Register 2: 0xF0
Register 3: 0x21
2
of
of
Frequency
Register
subcarrier
27
8/LINE
LOCKED
CLOCK
SEQUENCE
MHz
SC
0
Value
BIT
clk
Register
3
periods
6768
cycles
5 BITS
RESERVED
=
RESERVED
RESET BIT
⎛
⎜
⎝
227
1716
in
=
in
one
5 .
one
⎞
⎟
⎠
4
×
video
video
2
32
=
line
line
569408543
×
2
32
SC