adv7344 Analog Devices, Inc., adv7344 Datasheet - Page 51

• Manufacturer Part Number: adv7344
• Description: Multiformat Video Encoder Six 14-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

Typical F
Table 38 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
Table 38. Typical F
Subaddress
0x8C
0x8D
0x8E
0x8F
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
The ADV7344 supports a SD noninterlaced mode. Using this
mode, progressive inputs at twice the frame rate of NTSC and
PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input
into the ADV7344. The SD noninterlaced mode can be enabled
using Subaddress 0x88, Bit 1.
SC
Values
NTSC/PAL M SYSTEM
F
F
F
F
Description
SC
SC
SC
SC
SC
(525 LINES/60Hz)
(625 LINES/50Hz)
HSYNC
0
1
2
3
FIELD
PIXEL
DATA
Values
INPUT PIXELS
PAL SYSTEM
ANALOG
VIDEO
NTSC
0x1F
0x7C
0xF0
0x21
Y
END OF ACTIVE
VIDEO LINE
C
r
Y
F
F
4 CLOCK
4 CLOCK
EAV CODE
Figure 63. Square Pixel Mode EAV/SAV Embedded Timing
0
0
PAL B/D/G/H/I
0xCB
0x8A
0x09
0x2A
0
0
Figure 64. Square Pixel Mode Active Pixel Timing
X
Y
8
0
1
0
8
0
1
0
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ANCILLARY DATA
0
0
272 CLOCK
344 CLOCK
F
F
(HANC)
F
F
A
B
A
B
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Embedded EAV/SAV timing codes or external horizontal and
vertical synchronization signals provided on the S_HSYNC and
S_VSYNC pins can be used to synchronize the input pixel data.
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD
noninterlaced mode.
For 240p/59.94 Hz input, the ADV7344 should be configured for
NTSC operation, and Subaddress 0x88, Bit 1 should be set to 1.
For 288p/50 Hz input, the ADV7344 should be configured for
PAL operation and Subaddress 0x88, Bit 1 should be set to 1.
SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
The ADV7344 can be used to operate in square pixel mode
(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of
24.5454 MHz is required. Alternatively, for PAL operation, an input
clock of 29.5 MHz is required. The internal timing logic adjusts
accordingly for square pixel mode operation. In square pixel mode,
the timing diagrams shown in Figure 63 and Figure 64 apply.
A
B
8
0
1
0
8
0
1
0
SAV CODE
4 CLOCK
F
F
4 CLOCK
START OF ACTIVE
0
0
NTSC = 236 CLOCK CYCLES
PAL = 308 CLOCK CYCLES
VIDEO LINE
0
0
X
Y
C
b
Cb
Y C
1280 CLOCK
1536 CLOCK
r
Y
Y
C
b
Y
Cr
C
r
Y
Y
C
b
ADV7344