adv7322 Analog Devices, Inc., adv7322 Datasheet - Page 44

• Manufacturer Part Number: adv7322
• Description: Multiformat 11-bit Hdtv Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7322
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state the horizontal
and vertical counters will remain reset. When this bit is set back to
0, the internal counters will commence counting again.
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
SD REAL-TIME CONTROL, SUBCARRIER RESET,
AND TIMING RESET
[Subaddress 0x44, Bits 2 and 1]
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 0x44, Bits 1 and 2], the ADV7322 can be used in (a)
timing reset mode, (b) subcarrier phase reset mode, or (c) RTC
mode.
a.
A timing reset is achieved in a low-to-high transition
on the RTC_SCR_TR pin (Pin 31). In this state, the
horizontal and vertical counters will remain reset.
Upon releasing this pin (set to low), the internal
counters will commence counting again, the field
count will start on Field 1, and the subcarrier phase
will be reset.
The minimum time the pin must be held high is one
clock cycle; otherwise, this reset signal might not be
recognized. This timing reset applies to the SD timing
counters only.
DISPLAY
307
NO TIMING RESET APPLIED
TIMING RESET APPLIED
307
DISPLAY
310
1
START OF FIELD 1
2
3
Figure 59. Timing Reset Timing Diagram
313
4
START OF FIELD 4 OR 8
Rev. PrA | Page 44 of 88
5
6
F
7
SC
PHASE = FIELD 1
b.
c.
In subcarrier phase reset, a low-to-high transition on
the RTC_SCR_TR pin (Pin 31) will reset the
subcarrier phase to zero on the field following the
subcarrier phase reset when the SD RTC/TR/SCR
control bits at Address 0x44 are set to 01.
This reset signal must be held high for a minimum of
one clock cycle.
Since the field counter is not reset, it is recommended
that the reset signal is applied in Field 7 [PAL] or Field
3 [NTSC]. The reset of the phase will then occur on
the next field, i.e., Field 1, being lined up correctly with
the internal counters. The field count register at
Address 0x7B can be used to identify the number of
the active field.
In RTC mode, the ADV7322 can be used to lock to an
external video source. The real-time control mode
allows the ADV7322 to automatically alter the
subcarrier frequency to compensate for line length
variations. When the part is connected to a device that
outputs a digital data stream in the RTC format, such
as an ADV7183A video decoder (see Figure 61), the
part will automatically change to the compensated
subcarrier frequency on a line by line basis. This
digital data stream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles
long. Write 0x00 into all four subcarrier frequency
registers when this mode is used.
21
F
320
SC
PHASE = FIELD 4 OR 8
Preliminary Technical Data
TIMING RESET PULSE