adv7718 Analog Devices, Inc., adv7718 Datasheet - Page 13

• Manufacturer Part Number: adv7718
• Description: Integrated Digital Ccir-601 Pal/ntsc Video Encoder
• Manufacturer: Analog Devices, Inc.

PIXEL TIMING DESCRIPTION
The ADV7177/ADV7178 can operate in either 8-bit or 16-bit
YCrCb Mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
OSD
The ADV7177 supports OSD. There are twelve 8-bit OSD regis-
ters, loaded with data from the four most significant bits of Y, Cb,
Cr input pixel data bytes. A choice of eight colors can, therefore,
be selected via the OSD_0, OSD_1, OSD_2 pins, each color
being a combination of 12 bits of Y, Cb, Cr pixel data. The
display is under control of the OSD_EN pin. The OSD window
can be an entire screen or just one pixel, its size may change by
using the OSD_EN signal to control the width on a line-by-line
basis. Figure 4 illustrates OSD timing on the ADV7177.
VIDEO TIMING DESCRIPTION
The ADV7177/ADV7178 is intended to interface to off-the-shelf
MPEG1 and MPEG2 decoders. Consequently, the ADV7177/
ADV7178 accepts 4:2:2 YCrCb pixel data via a CCIR-656 pixel
port, and has several video timing modes of operation that allow it
FILTER SELECTION
NTSC
PAL
NTSC
PAL
NTSC
PAL
NTSC/PAL
NTSC
PAL
FILTER SELECTION
MR04
0
0
0
0
1
1
1
MR03
CUTOFF (MHz)
PASSBAND
0
0
1
1
0
1
1
1.0
1.3
CUTOFF (MHz)
PASSBAND
2.3
3.4
1.0
1.4
4.0
2.3
3.4
RIPPLE (dB)
PASSBAND
0.085
0.04
RIPPLE (dB)
PASSBAND
0.026
0.098
0.085
0.107
0.150
0.054
0.106
CUTOFF (MHz)
STOPBAND
to be configured as either system master video timing generator
or a slave to the system video timing generator. The ADV7177/
ADV7178 generates all of the required horizontal and vertical
timing periods and levels for the analog video outputs.
The ADV7177/ADV7178 calculates the width and placement of
analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
In addition, the ADV7177/ADV7178 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct location
for the new clock frequencies.
The ADV7177/ADV7178 has four distinct master and four
distinct slave timing configurations. Timing Control is established
with the bidirectional SYNC, BLANK, and FIELD/VSYNC
pins. Timing Mode Register 1 can also be used to vary the timing
pulsewidths and where they occur in relation to each other.
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on those
lines of VBI that do not bear line sync or pre-/post-equalization
pulses (see TPCs). This mode of operation is called “Partial Blank-
ing” and is selected by setting MR31 to 1. It allows the insertion of
any VBI data (Opened VBI) into the encoded output waveform.
This data is present in digitized incoming YCbCr data stream
(e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI
may be blanked (no VBI data inserted) on these lines by setting
MR31 to 0.
3.2
4.0
CUTOFF (MHz)
STOPBAND
7.0
7.3
3.57
4.43
7.5
7.0
7.3
ATTENUATION (dB)
STOPBAND
>
>
40
40
ATTENUATION (dB)
STOPBAND
>
>
>
>
>
>
>
54
50
27.6
29.3
40
54
50.3
ADV7177/ADV7178
ATTENUATION @
1.3MHz (dB)
0.3
0.02
F
4.2
5.0
2.1
2.7
5.35
4.2
5.0
3 dB
F
2.05
2.45
3 dB