adv7718 Analog Devices, Inc., adv7718 Datasheet - Page 21

• Manufacturer Part Number: adv7718
• Description: Integrated Digital Ccir-601 Pal/ntsc Video Encoder
• Manufacturer: Analog Devices, Inc.

To control the various devices on the bus, the following protocol
must be followed: First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
start condition and shift the next eight bits (7-bit address+ R/W
bit). The bits transfer from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at this
point and maintain an idle condition. The idle condition is where
the device monitors the SDATA and SCLOCK lines waiting for
the start condition and the correct transmitted address. The R/W
bit determines the direction of the data. A Logic “0” on the LSB
of the first byte means that the master will write information to
the peripheral. A Logic “1” on the LSB of the first byte means
that the master will read information from the peripheral.
The ADV7177/ADV7178 acts as a standard slave device on the bus.
The data on the SDATA pin is 8 bits long, supporting the 7-bit
addresses, plus the R/W bit. The ADV7178 has 36 subaddresses
and the ADV7177 has 31 subaddresses to enable access to the
internal registers. It therefore interprets the first byte as the device
address and the second byte as the starting subaddress. The sub-
addresses auto increment allows data to be written to or read from
the starting subaddress. A data transfer is always terminated by a
stop condition. The user can also access any unique subaddress
register on a one-by-one basis without having to update all the
registers. There is one exception. The subcarrier frequency
registers should be updated in sequence, starting with Subcarrier
Frequency Register 0. The auto increment function should then
be used to increment and access Subcarrier Frequency Registers
1, 2 and 3. The subcarrier frequency registers should not be
accessed independently.
SEQUENCE
SEQUENCE
WRITE
READ
S
S
S = START BIT
P = STOP BIT
SLAVE ADDR A(S)
SLAVE ADDR A(S)
LSB = 0
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
SUB ADDR
SUB ADDR
A(S)
A(S) S SLAVE ADDR A(S)
DATA
LSB = 1
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high period,
the user should issue only one start condition, one stop condition or
a single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADV7177/ADV7178
will not issue an acknowledge and will return to the idle condition.
If, in auto-increment mode, the user exceeds the highest subad-
dress, the following action will be taken:
1. In Read Mode, the highest subaddress register contents will
2. In Write Mode, the data for the invalid byte will not be loaded
Figure 22 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 23 shows bus write and read sequences.
SCLOCK
SDATA
A(S)
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDATA line is not pulled low on the
ninth pulse.
into any subaddress register, a no-acknowledge will be issued
by the ADV7177/ADV7178 and the part will return to the
idle condition.
START ADDR R/W ACK SUBADDRESS ACK
S
DATA
1–7
DATA
8
A(M)
9
A(S) P
1–7
ADV7177/ADV7178
8
DATA
9
A(M)
1–7
DATA
P
8
ACK
9
STOP
P