ca3310 Intersil Corporation, ca3310 Datasheet
ca3310
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ca3310 Summary of contents
Page 1
... CMOS, 10-Bit, A/D Converters with Internal Track and Hold Description The Intersil CA3310 is a fast, low power, 10-bit successive approximation analog-to-digital converter, with microprocessor- compatible outputs. It uses only a single supply and typically draws just 3mA when operating at 5V. It can accept full rail-to-rail input signals, and features a built-in track and hold ...
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... REF 8C 50 SUBSTRATE RESISTANCE 16C REF CA3310, CA3310A CONTROL AND TIMING 10-BIT 10-BIT EDGE SUCCESSIVE TRIGGERED APPROXIMATION “D” REGISTER LATCH 6-7 STRT R EXT CLOCK CLK DRDY Q DRST CLK CLR OEM D9 (MSB ...
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... ADJUST GAIN 100 0 CA3140 - - R4 10K 1 4 0.1 A -1V 100 TO -15V INPUT RANGE 10V -2.5V TO +2.5V -5V TO +5V CA3310, CA3310A + 4.7 F TAN 4. REF + 75V 4.7 F TAN A 5K 28. REF CA3310 + +15V OPTIONAL CLAMP ...
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... Input - Full-Scale Range Input Bandwidth DIGITAL INPUTS DRST, OEL, OEM, STRT, CLK High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Input Current CA3310, CA3310A Thermal Information -0. +7V Thermal Resistance (Typical, Note 0.5V PDIP Package . . . . . . . . . . . . . . . . . . . . . ...
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... Analog Supply Rejection Reference Input Current TEMPERATURE DEPENDENCY Offset Drift Gain Drift Internal Clock Speed NOTES (-) removal time means the signal can be removed after the reference signal. 2. Parameter not tested, but guaranteed by design or characterization. CA3310, CA3310A 5V 4.608V REF ...
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... OFF TO HIGH OFF TO LOW FIGURE 2. OUTPUT ENABLE/DISABLE TIMING DIAGRAM 13 CLK (INTERNAL) xxxxxxx xxxxxxx xxxxxxx STRT xxxxxxx xxxxxxx DRDY HOLD INPUT FIGURE 3. STRT PULSED LOW, DRST TIED HIGH, INTERNAL CLOCK CA3310, CA3310A HIGH t DRDY D2 DATA HOLD TRACK N t APR ...
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... V DD 700 600 4V 500 400 3V 300 200 100 0 SHORT 10 100 EXTERNAL RESISTANCE (k FIGURE 6. INTERNAL CLOCK FREQUENCY vs EXTERNAL RESISTANCE CA3310, CA3310A STRT R xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx TRACK 13 1 xxxxxxxxxxxxxxxxxx CLK xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx DON’T CARE OR xxxxxxxxxxxxxxxxxx t DRST ...
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... VOLTAGE (V) REF FIGURE 10 CURRENT vs V REF OFFSET GAIN 0 0 CLOCK FREQUENCY (MHz) FIGURE 12. NORMALIZED GAIN, OFFSET, INTEGRAL AND DIFFERENTIAL LINEARITY ERRORS vs CLOCK SPEED CA3310, CA3310A (Continued) +60 + +40 + + -10 - FIGURE 9. AVERAGE INPUT CURRENT vs INPUT VOLTAGE ...
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... REF 3.456 4 REF REF ( LSB 4.6035 REF REF NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. CA3310, CA3310A (Continued 5V, OPEN 4V, OPEN 2.5 3.0 3.5 -50 FIGURE 15 ...
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... The conversion cycle is now complete. Clock The CA3310 can operate either from its internal clock or from one externally supplied. The CLK pin functions either as the clock output or input. All converter functions are syn- chronous with the rising edge of the clock signal. ...
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... R STRT set-up OUTPUT SU CODE DRDY) drop D4 FIGURE 17. DIFFERENTIAL LINEARITY ERROR The CA3310 output should change from a code of 000 001 at an input voltage change from a code of 3FE ( LSB). Any differences between the actual and REF expected input voltages that cause these transitions are the offset and gain errors, respectively ...
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... OUTPUT CODE (HEX) 001 000 OFFSET POINT FIGURE 19. NORMALIZED GAIN, OFFSET, INTEGRAL AND DIFFERENTIAL LINEARITY ERRORS vs REFERENCE VOLTAGE CA3310, CA3310A EXPECTED TRANSFER CURVE OFFSET ERROR 1 2 1022 1024 1024 1024 INPUT VOLTAGE AS A FRACTION OF (V REF FIGURE 18 ...
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... Note that the frequency to be rejected scales with the clock: the 100Hz rejection with a 100kHz clock would be roughly equivalent to the 1kHz rejection with a 1MHz clock. The supply current for the CA3310 is dependent on clock frequency, supply voltage, and temperature. Figure 14 shows the typical current versus frequency and voltage, while Figure 15 shows it versus temperature and voltage ...
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... Figure 21 illustrates this application. The CA3310 is connected free run. The Data Ready signal is shifted through a CD74HC175, and at the low-going clock edge just before the sample would end, is used to hold the clock low ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 CA3310, CA3310A EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...