ca3310 Intersil Corporation, ca3310 Datasheet - Page 11

• Manufacturer Part Number: ca3310
• Description: Cmos, 10-bit, A/d Converters With Internal Track And Hold
• Manufacturer: Intersil Corporation

will shut off after entering period 2. The input will continue to
track the DRDY output will remain high during this time.
A low signal applied to STRT (at least t
now initiate a new conversion. The STRT signal (after a
delay of t
(after a delay of t
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
The input will continue to track until the end of period 3, the
same as when free-running.
Figure 4 illustrates the same operation as above, but with an
external clock. If STRT is removed (at least t
clock period 1, and not reapplied during that period, the
clock will continue to cycle in period 2. A low signal applied
to STRT will drop the DRDY flag as before, and with the first
positive-going clock edge that meets the t
time, the converter will continue with clock period 3.
The DRDY flag output, as described previously, goes active
at the start of period 1, and drops at the start of period 2 or
upon a new STRT command, whichever is later. It may also
be controlled with the DRST (Data Ready Reset) input.
Figure 5 depicts this operation.
DRST must be removed (at least t
of period 1 to allow DRDY to go high. A low level on DRST
(at least t
DRDY.
Analog Input
The analog input pin is a predominantly capacitive load that
changes between the track and hold periods of a conversion
cycle. During hold, clock period 4 through 13, the input
loading is leakage and stray capacitance, typically less than
0.1 A and 20pF.
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have low
enough impedance to dissipate the charge by the end of the
tracking period. The amount of charge is dependent on supply
and input voltages. Figure 8 shows typical peak input currents
for various supply and input voltages, while Figure 9 shows
typical average input currents. The average current is also pro-
portional to clock frequency, and should be scaled accordingly.
During tracking, the input appears as approximately a 300pF
capacitor in series with 330
full-scale input swing would settle to
time constants. Doing continuous conversions with a 1MHz
clock provides 3 s of tracking time, so up to 1k
source impedance (400ns time constant) would allow proper
settling of a step input.
If the clock was slower, or the converter was not restarted
immediately (causing a longer sample lime), a higher source
impedance could be used.
The CA3310s low-input time constant also allows good
tracking of dynamic input waveforms. The sampling rate with
a 1MHz clock is approximately 80kHz. A Nyquist rate
(f
attenuation and a phase lag of only 1.5 degrees.
SAMPLE
W
D3
/2) input sine wave of 40kHz would have negligible
DRST wide) will (after a delay of t
DRDY) will cause the DRDY flag to drop, and
D
CLK) cause the clock to restart.
for a 100ns time constant. A
R
1
DRST) before the start
/
2
LSB (
W
SU
STRT wide) can
R
D4
1
STRT) before
/
STRT set-up
2048
DRDY) drop
CA3310, CA3310A
of external
) in 7RC
6-16
Accuracy Specifications
The CA3310 accepts an analog input between the values of
V
output codes. Each code should exist as the input is varied
through a range of
1 LSB of input voltage. A differential Iinearity error, illustrated
in Figure 17, occurs if an output code occurs over other than
the ideal (1 LSB) input range. Note that as long as the error
does not reach -1 LSB, the converter will not miss any codes.
The CA3310 output should change from a code of 000
001
change from a code of 3FE
(V
expected input voltages that cause these transitions are the
offset and gain errors, respectively. Figure 18 illustrates
these errors.
As the input voltage is increased linearly from the point that
causes the 000
the 3FE
increase linearly. Any deviation from this input-to-output cor-
respondence is integral linearity error, illustrated in Figure 19.
Note that the integral linearity is referenced to a straight line
drawn through the actual end points, not the ideal end
points. For absolute accuracy to be equal to the integral lin-
earity, the gain and offset would have to be adjusted to ideal.
Offset and Gain Adjustments
The V
the analog input range, are the only means of doing offset or
gain adjustments. In a typical system, the V
returned to a clean ground, and offset adjustment done on
an input amplifier. V
V
modate an input source that can’t drive down to ground. There
are current pulses that occur, however, during the successive
approximation part of a conversion cycle, as the charge-balanc-
ing capacitors are switched between V
that reason, V
Figure 10 shows peak and average V
REF
REF
OUTPUT
REF
CODE
16
- could be raised from ground to adjust offset or to accom-
- and V
REF
+ -1 LSB). Any differences between the actual and
at an input voltage of (V
FIGURE 17. DIFFERENTIAL LINEARITY ERROR
16
+ and V
to 3FF
REF
REF
16
+, and quantizes it into one of 2
16
to 001
REF
- and V
1
REF
/
A = IDEAL 1 LSB STEP
B-A = + DIFFERENTIAL LINEARITY ERROR
A-C = - DIFFERENTIAL LINEARITY ERROR
1024
transition, the output code should also
- pins, references for the two ends of
+ would then be adjusted for gain.
16
X (V
transition to the point that causes
REF
INPUT VOLTAGE
C
ACTUAL
TRANSFER
CURVE
REF
16
REF
+ should be well bypassed.
TRANSFER
UNIFORM
to 3FF
+ - V
CURVE
- +1 LSB). It should also
REF
REF
A
B
REF
+ current.
16
- and V
-), referred to as
at an input of
REF
10
- might be
REF
or 1024
+. For
16
to