ca3310 Intersil Corporation, ca3310 Datasheet - Page 10

• Manufacturer Part Number: ca3310
• Description: Cmos, 10-bit, A/d Converters With Internal Track And Hold
• Manufacturer: Intersil Corporation

Device Operation
The CA3310 is a CMOS 10-bit, analog-to-digital converter
that uses capacitor-charge balancing to successively
approximate the analog input. A binarily weighted capacitor
network forms the D-to-A “Heart” of the device. See the
Functional Diagram of the CA3310.
The capacitor network has a common node which is connected
to a comparator. The second terminal of each capacitor is indi-
vidually switchable to the input, V
During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input.
The comparator is being auto-balanced at its trip point, thus
setting the voltage at the capacitor common node.
During the fourth period, all capacitors are disconnected
from the input, the one representing the MSB (D9) is con-
nected to the V
to V
balance out, will represent whether the input was above or
below
At the end of the fourth period, the comparator output is
stored and the MSB capacitor is either left connected to
V
This allows the next comparison to be at either
(V
At the end of periods 5 through 12, capacitors representing
the next to MSB (D8) through the next to LSB (D1) are
tested, the result stored, and each capacitor either left at
V
At the end of the 13th period, when the LSB (D0) capacitor is
tested, D0 and all the previous results are shifted to the out-
put registers and drivers. The capacitors are reconnected to
the input, the comparator returns to the balance state, and
the data-ready output goes active. The conversion cycle is
now complete.
Clock
The CA3310 can operate either from its internal clock or
from one externally supplied. The CLK pin functions either
as the clock output or input. All converter functions are syn-
chronous with the rising edge of the clock signal.
Figure 16 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
wiring capacitance should be kept to a minimum.
OPTIONAL
EXTERNAL
CLOCK
REF
REF
REF
REF
+ (if the comparator was high) or returned to V
+ or at V
1
+ - V
/
2
-. The capacitor-common node, after the charges
of (V
REF
REF
REF
FIGURE 16. CLOCK CIRCUITRY
OPTIONAL
CLOCK
ADJUST
REF
-).
-.
+ - V
+ terminal, and the remaining capacitors
CLK
R
EXT
REF
).
REF
50K
INTERNAL
ENABLE
+ or V
REF
100K
-.
3
CA3310, CA3310A
INTERNAL
CLOCK
/
4
or
18pF
REF
1
/
4
of
-.
6-15
The R
frequency by connecting a resistor between R
Figure 6 shows the typical relationship between the resistor
and clock speed, while Figure 7 shows clock speed versus
temperature and supply voltage.
The internal clock will shut down if the A/D is not restarted after
a conversion. This is described under Control Timing. The clock
could also be shut down with an open collector driver applied to
the CLK pin. This should only be done during the sample por-
tion (the first three periods) of a conversion cycle, and might be
useful for using the device as a digital sample and hold: this is
described further under Applications.
If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again only during the sam-
ple portion of a conversion cycle. At other times, it must be
above the minimum frequency shown in the specifications.
If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 13) of the A/D, the
output might be invalid due to balancing capacitor droop.
An external clock must also meet the minimum t
t
cause an internal miscount and invalidate the results.
Control Signals
The CA3310 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate conver-
sions, or if STRT is tied low, may be allowed to free-run. In
the free-running mode, illustrated in Figure 1, each
conversion takes 13 clock periods.
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
place. After the start of the next period 1 (specified by T
data), the output is updated.
The DRDY (Data Ready) status output goes high (specified
by t
low (specified by t
DRDY may also be asynchronously reset by a low on DRST
(to be discussed later).
If the output data is to be latched externally by the DRDY
signal, the trailing edge of DRDY should be used: there is no
guaranteed set-up time to the leading edge.
The 10 output data bits are available in parallel on three-
state bus driver outputs. When low, the OEM input enables
the most significant byte (D2 through D9) while the OEL
input enables the two least significant bits (D0, D1). t
t
tively. See Figure 2.
When the STRT input is used to initiate conversions,
operation is slightly different depending on whether an
internal or external clock is used.
Figure 3 illustrates operation with an internal clock. If the
STRT signal is removed (at least t
period 1, and is not reapplied during that period, the clock
HIGH
DIS
D1
specify the output enable and disable times, respec-
times shown in the specifications. A violation may
EXT
DRDY) after the start of clock period 1, and returns
pin allows adjusting of the internal clock
D2
DRDY) after the start of clock period 2.
R
STRT) before clock
EXT
and CLK.
LOW
EN
and
and
D