xcr3064xl Xilinx Corp., xcr3064xl Datasheet - Page 4

• Manufacturer Part Number: xcr3064xl
• Description: Xcr3064xl 64 Macrocell Cpld ,
• Manufacturer: Xilinx Corp.

XCR3064XL 64 Macrocell CPLD
Timing Model
The XPLA3 architecture follows a simple timing model that
allows deterministic timing in design and redesign. The
basic timing model is shown in
the XPLA3 CPLD is the ability to have up to 48 product term
inputs into a single macrocell and maintain consistent tim-
ing. This is achieved through the use of a fully populated
PLA (Programmable AND Programmable OR Array) which
also has the ability to share product terms and only use the
required amount of product terms per macrocell. There is a
fast path (T
4
LOGI1
) into the macrocell which is used if there is
T
T
T
GCK
FIN
IN
Figure
T
2. One key feature of
T
LOGI1,2
LOGI3
Figure 2: XPLA3 Timing Model
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T
F
T
a single product term. The T
product term timing. For optimization of logic, the XPLA3
CPLD architecture includes a Fold-back NAND path
(T
as an Input Register (T
control terms (T
the macrocell registers in different logic blocks. There is
also slew rate control and output enable control on a per
macrocell basis.
UDA
LOGI3
). There is a fast input path to each macrocell if used
UDA
DLT
CE
S/R
) that can be used for synchronization of
FIN
). XPLA3 also includes universal
Preliminary Product Specification
LOGI2
Q
DS017 (v1.1) August 30, 2000
path is used for multiple
T
T
T
OUT
EN
SLEW
DS017_02_042800
R