xa2c32a Xilinx Corp., xa2c32a Datasheet
xa2c32a
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xa2c32a Summary of contents
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... Global set/reset - Abundant product term clocks, output enables and set/resets - Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - Advanced design security Table 1: CoolRunner-II Automotive CPLD Family Parameters XA2C32A Macrocells 32 Max I (ns) 5 (ns) 2 ...
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... The I/O banks are groupings of I/O pins using any one of a sub- set of compatible voltage standards that share the same V level. (See CCIO Automotive CPLD I/O standards.) XA2C32A XA2C64A ware, which exploits the 100% routability of the Program- mable Logic Array within each FB. This extremely robust building block delivers the industry’ ...
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R Figure 1 shows the high-level architecture whereby Func- tion Blocks attach to pins and interconnect to each other within the internal interconnect matrix. Each FB contains 16 MC1 I/O Pin MC2 I/O Pin 16 MC16 I/O Pin 16 JTAG ...
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CoolRunner-II Automotive CPLD Product Family term budget is reached, there is a small interconnect timing penalty to route signals to another FB to continue creating logic. Xilinx design software handles all this automatically. Macrocell The CoolRunner-II Automotive extremely efficient and ...
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R Advanced Interconnect Matrix (AIM) The Advanced Interconnect Matrix is a highly connected low power rapid switch. The AIM is directed by the software to deliver set of 40 signals to each FB for the cre- ation ...
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CoolRunner-II Automotive CPLD Product Family reduce their system current even more by selectively dis- abling circuitry not being used. The patented DataGATE technology was developed to per- mit a straightforward approach to additional power reduc- tion. Each I/O pin has ...
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R purpose I/O if they are not needed as global signals. The DataGATE assertion rail is also a global signal. DS090_07_101001 Figure 6: Global Clocks (GCK), Sets/Resets (GSR) and Output Enables (GTS) GCK2 CDRST DS315 (v1.1) October 31, 2006 Product ...
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CoolRunner-II Automotive CPLD Product Family CLK_CT PTC Figure 8: Macrocell Clock Chain with DualEDGE Option Shown GCK2 CDRST Figure 9: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option Design Security Designs can be secured during programming to prevent either ...
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R Timing Model Figure 10 shows the CoolRunner-II CPLD timing model. It represents one aspect of the overall architecture from a tim- ing viewpoint. Each little block is a time delay that a signal will incur if the signal passes ...
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CoolRunner-II Automotive CPLD Product Family Programming The programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester simple microprocessor interface that ...
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R V CCINT 1.3V 3.8 V (Typ) (Typ Quiescent User Operation Power State Initialization Transition of User Array Figure 11: Device Behavior During Power Up Table 7: I/O Power-Up Characteristics Device Circuitry IOB Bus-Hold/Weak Pullup Device Outputs Device ...
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... The I/O voltage may never exceed 4.0V. 4. For soldering guidelines and thermal considerations, see the packages, see XAPP427. CoolRunner-II Automotive Data Sheets http://direct.xilinx.com/bvdocs/publications/ds552.pdf (XA2C32A Datasheet) http://direct.xilinx.com/bvdocs/publications/ds553.pdf (XA2C64A Datasheet) http://direct.xilinx.com/bvdocs/publications/ds554.pdf (XA2C128 Datasheet) Quality and Reliability Parameters ...
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not rely on the I/O states before the CPLD configures. 8. Use a voltage regulator which can provide sufficient current during device power up rule of thumb, the regulator needs to provide at least three ...
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... The following table shows the revision history for this document. Date Version 10/18/04 1.0 Initial Xilinx release 10/31/06 1.1 Re-released with individual data sheets for XA2C32A, XA2C64A, XA2C128, XA2C256, and XA2C384 14 http://direct.xilinx.com/bvdocs/appnotes/xapp389.pdf (Powering CoolRunner-II) http://direct.xilinx.com/bvdocs/appnotes/xapp393.pdf (8051 Microcontroller Interface) http://direct.xilinx.com/bvdocs/appnotes/xapp394.pdf (Interfacing with Mobile SDRAM) http://direct ...