adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 24

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21267
Memory Read–Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the ADSP-21267
is accessing external memory space.
Table 18. 8-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
D = (Data Cycle Duration) x t
H= t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
DAD
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
ADRH
CCLK
(if a hold cycle is specified, else H = 0)
Address/Data [7:0] Setup Before RD High
Address/Data [7:0] Hold After RD High
Address [15:8] to Data Valid
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data [15:0] Setup Before ALE Deasserted
Address/Data [15:0] Hold After ALE Deasserted
ALE Deasserted
RD Pulse Width
Address/Data [15:8] Hold After RD High
AD[15:8
AD[7:0]
ALE
WR
RD
CCLK
]
1
to Address/Data[7:0] In High Z
PRELIMINARY TECHNICAL DATA
VALID ADDRESS
VALID ADDRESS
t
ADAS
t
Figure 17. Read Cycle For 8-bit Memory Timing
ALEW
Rev. PrA | Page 24 of 44 | January 2004
t
ADAH
t
ALEHZ
1
t
ALERW
1
Min
3.3
0
2 x t
1 x t
2.5 x t
0.5 x t
0.5 x t
D – 2
0.5 x t
CCLK
CCLK
t
CCLK
CCLK
CCLK
CCLK
DAD
– 2
– 1
VALID ADDRESS
– 2.0
– 0.8
– 0.8
– 1 + H
VALID DATA
t
RW
t
DRS
t
t
DRH
ADRH
Max
D + 0.5 x t
0.5 x t
CCLK
+ 3.0
CCLK
– 3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns