adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 3

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

GENERAL DESCRIPTION
The ADSP-21267 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices' Super Har-
vard Architecture. The ADSP-21267 is source code compatible
with the ADSP-2136x, and ADSP-2116x DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin-
gle-Instruction, Single-Data) mode. Like other SHARC DSPs,
the ADSP-21267 is a 32-bit/40-bit floating-point processor opti-
mized for high performance audio applications with its dual-
ported on-chip SRAM, mask-programmable ROM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
Digital Audio Interface (DAI).
As shown in the Functional Block Diagram on page 1, the
ADSP-21267 uses two computational units to deliver a signifi-
cant performance increase over previous SHARC processors on
a range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the ADSP-21267 DSP achieves an
instruction cycle time of 6.6 ns at 150 MHz. With its SIMD
computational hardware, the ADSP-21267 can perform 900
MFLOPS running at 150 MHz.
Table 1. ADSP-21267 Benchmarks (at 150 MHz)
1
The ADSP-21267 continues SHARC’s industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 1M bit dual-ported SRAM memory, 3M bits
dual-ported ROM, an I/O processor that supports 18 DMA
channels, four serial ports, an SPI interface, an external parallel
bus, and Digital Audio Interface (DAI).
The block diagram of the ADSP-21267
following architectural features:
Table 1
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3x3] x [3x1]
[4x4] x [4x1]
Divide (y/x)
Inverse Square Root
Assumes two files in multichannel SIMD mode.
• Two processing elements, each containing an ALU, Multi-
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
plier, Shifter and Data Register File
transfers between memory and the core at every core pro-
cessor cycle
shows performance benchmarks for the ADSP-21267.
1
1
PRELIMINARY TECHNICAL DATA
on page
Speed
(at 150 MHz)
30 ns
53.3 ns
20 ns
30 ns
3.3 ns
13.3 ns
1, illustrates the
Rev. PrA | Page 3 of 44 | January 2004
s
Figure 2 on page 4
using the precision clock generator to interface with an I
and an I
port would generate itself. Many other SRU configurations are
possible.
ADSP-21267 FAMILY CORE ARCHITECTURE
The ADSP-21267 is code compatible at the assembly level with
the ADSP-2136x, ADSP-2116x, and with the first generation
ADSP-2106x SHARC DSPs. The ADSP-21267 shares architec-
tural features with the ADSP-2136x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.
SIMD Computational Engine
The ADSP-21267 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive audio algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
• Three Programmable Interval Timers with PWM Genera-
• On-Chip dual-ported SRAM (1 Mbit)
• On-Chip dual-ported, mask-programmable ROM
• JTAG test access port
• 8- or 16-bit Parallel port that supports interfaces to off-chip
• DMA controller
• Four full-duplex serial ports
• SPI-compatible interface
• Digital Audio Interface that includes two precision clock
tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities
(3 Mbits)
memory peripherals
generators (PCG), an input data port (IDP), four serial
ports, eight serial interfaces, a 20-bit synchronous parallel
input port, 10 interrupts, six flag outputs, six flag inputs,
three timers, and a flexible signal routing unit (SRU)
2
S DAC with a much lower jitter clock than the serial
shows one sample configuration of a SPORT
ADSP-21267
2
S ADC