adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 6

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21267
Left-justified Sample Pair Mode is a mode where in each Frame
Sync cycle two samples of data are transmitted/received — one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the Left-justified Sample Pair
and I
monly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four Left-justified Sample Pair or I
devices) per serial port, with a maximum of up to 16 audio
channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
• I
• Left-justified sample pair mode
2
2
S protocols (I
S mode
0x0007 E000 - 0x0007 FFFF
0x0004 2000 - 0x0005 7FFF
0x0005 8000 - 0x0002 FFFF
0x0005 3000 - 0x0005 FFFF
0x0007 8000 - 0x0007 DFFF
0x0000 0000 - 0x0003 FFFF
0x0004 0000 - 0x0004 1FFF
0x0006 0000 - 0x0006 1FFF
0x0006 2000 - 0x0007 7FFF
BLOCK 0 SRAM (0.5 Mbit)
BLOCK 1 SRAM (0.5 Mbit)
BLOCK 0 ROM (1.5 mbit)
BLOCK 1 ROM (1.5 mbit)
ADDRESSING
LONG WORD
IOP REGISTERS
RESERVED
RESERVED
RESERVED
RESERVED
2
S is an industry standard interface com-
2
S channels (using two stereo
PRELIMINARY TECHNICAL DATA
INTERNAL MEMORY
EXTERNAL MEMORY
Rev. PrA | Page 6 of 44 | January 2004
Figure 3. ADSP-21267 Memory Map
0x0300 0000 - 0x3FFF FFFF
0x000B C000 - 0x000B FFFF
0x0020 0000 - 0x00FF FFFF
0x0100 0000 - 0x02FF FFFF
0x000B 0000 - 0x000B BFFF
0x000F C000 - 0x000F FFFF
0x000C 0000 - 0x000C 3FFF
0x000F 0000 - 0x000F BFFF
0x0008 4000 - 0x000A FFFF
0x000C 4000 - 0x000E FFFF
0x0000 0000 - 0x0003 FFFF
0x0008 0000 - 0x0008 3FFF
BLOCK 1 SRAM (0.5 Mbit)
BLOCK 0 SRAM (0.5 Mbit)
NORMAL WORD
BLOCK 0 ROM (1.5 mbit)
BLOCK 1 ROM (1.5 mbit)
ADDRESSING
ADDRESS SPACE 1
SPACE
EXTERNAL DMA
IOP REGISTERS
RESERVED
SPACE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
32 bits. For the Left-justified Sample Pair and I
word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional -law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.
Serial Peripheral (Compatible) Interface
Serial Peripheral Interface (SPI) is an industry standard syn-
chronous serial link, enabling the ADSP-21267 SPI-compatible
port to communicate with other SPI-compatible devices. SPI is
an interface consisting of two data pins, one device select pin,
and one clock pin. It is a full-duplex synchronous serial inter-
face, supporting both master and slave modes. The SPI port can
operate in a multi-master environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
1 EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE
BY THE CORE. DMA MUST BE USED TO READ OR WRITE
TO THIS MEMORY USING THE SPI OR PARALLEL PORT.
2 BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE
3 BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE
(0x000E 0000 - 0x000E AAA).
(0x000A 0000 - 0x000A AAAA).
0x0017 8FFF - 0x0017 FFFF
0x0010 8000 - 0x0015 FFFF
0x001E 0000 - 0x001F 7FFF
0x0018 8000 - 0x001D FFFF
0x0016 0000 - 0x0017 7FFF
0x0018 0000 - 0x0018 7FFF
0x0000 0000 - 0x0003 FFFF
0x0010 0000 - 0x0010 7FFF
BLOCK 1 SRAM (0.5 Mbit)
BLOCK 0 SRAM (0.5 Mbit)
BLOCK 1 ROM (1.5 mbit)
BLOCK 0 ROM (1.5 mbit)
SHORT WORD
ADDRESSING
IOP REGISTERS
RESERVED
RESERVED
RESERVED
RESERVED
0x000
2
S modes, data-