dsp56367 Freescale Semiconductor, Inc, dsp56367 Datasheet - Page 30

• Manufacturer Part Number: dsp56367
• Description: Dsp56367 24-bit Audio Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Phase Lock Loop (PLL) Characteristics
3.8
3-6
1
2
3
4
1
V
PLL external capacitor (PCAP pin to V
No.
• @ MF ≤ 4
• @ MF > 4
Measured at 50% of the input transition.
The maximum value for PLL enabled is given for minimum V
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
The maximum value for PLL enabled is given for minimum V
4
7
CO
C
C
PCAP
PCAP
frequency when PLL enabled (MF × E
(MF x 680)-120, for MF ≤ 4, or
MF x 1100, for MF > 4.
EXTAL cycle time
Instruction cycle time = I
• With PLL disabled
• With PLL enabled
• With PLL disabled
• With PLL enabled
is the value of the PLL capacitor (connected between the PCAP pin and V
can be computed from one of the following equations:
Phase Lock Loop (PLL) Characteristics
Characteristics
2
CYC
Characteristics
= T
Table 3-5 Clock Operation (continued)
CCP
C
4
) (C
f
DSP56367 Technical Data, Rev. 2.1
Table 3-6 PLL Characteristics
× 2/PDF)
PCAP
1)
CO
CO
and maximum MF.
and maximum DF.
(MF × 580) − 100
MF × 830
Min
30
Symbol
I
ET
CCP
CYC
C
). The recommended value in pF for
(MF × 780) − 140
MF × 1470
13.33 ns
6.67 ns
6.7 ns
6.7 ns
Max
Min
300
Freescale Semiconductor
273.1 µs
8.53 µs
Max
MHz
∞
∞
Unit
pF