dsp56367 Freescale Semiconductor, Inc, dsp56367 Datasheet - Page 56

• Manufacturer Part Number: dsp56367
• Description: Dsp56367 24-bit Audio Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

1
2
3
4
5
6
7
8
Parallel Host Interface (HDI08) Timing
3-32
332
333
334
335
336
337
338
339
340
341
342
343
344
No.
See Host Port Usage Considerations in the DSP56367 User’s Manual.
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
V
The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.
This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
This timing is applicable only if two consecutive reads from one of these registers are executed.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
CC
= 1.8 V ± 5%; T
HCS assertion to output data valid
HCS hold time after data strobe deassertion
Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)
Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data
strobe assertion
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe
deassertion
Delay from read data strobe deassertion to host request assertion for “Last
Data Register” read
Delay from write data strobe deassertion to host request assertion for “Last
Data Register” write
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD = 0)
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD = 1, open drain Host Request)
Delay from DMA HACK deassertion to HOREQ assertion
Delay from DMA HACK assertion to HOREQ deassertion
Delay from DMA HACK assertion to HOREQ deassertion for “Last Data
Register” read or write
• Read
• Write
• For “Last Data Register” read
• For “Last Data Register” write
• For other cases
• HROD = 0
• HROD = 1, open drain Host Request
9
5
J
9
= –40°C to +95°C, C
4, 5, 10
5, 8, 10
Table 3-15 Host Interface (HDI08) Timing
Characteristics
5
5
5, 9, 10
DSP56367 Technical Data, Rev. 2.1
L
= 50 pF
5, 11
9
5, 9, 10, 11
1, 2, 3
1.5 × T
(continued)
2 × T
Expression
2 × T
C
T
—
—
—
—
—
—
—
—
—
—
C
C
+ 19.1
+ 19.1
C
Freescale Semiconductor
13.4
32.5
29.2
Min
0.0
4.7
3.3
4.7
3.3
6.7
0.0
—
—
—
—
—
0
150 MHz
300.0
300.0
Max
19.1
19.1
20.2
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns