saa7110 NXP Semiconductors, saa7110 Datasheet - Page 40

• Manufacturer Part Number: saa7110
• Description: One Chip Front-end 1 Ocf1
• Manufacturer: NXP Semiconductors

Philips Semiconductors
16.3.15 S
Table 25 I/O and clock control
16.3.16 S
Table 26 Control number 1
1995 Oct 18
General purpose switch (GPSW); data bit D0
Select chrominance input (CHRS); data bit D2
Output enable YUV-data (OEYC); data bit D3
Output enable horizontal/vertical synchronization (OEHV); data bit D4
Horizontal PLL clock (HPLL); data bit D7
Luminance delay compensation; steps in 2/LLC (YDEL); data bits D2, D1 and D0
Enable or disable of sync and clamp pulses; HSY and HCL (SCEN); data bit D4
SECAM cross colour reduction (SXCR); data bit D5
Field selection (FSEL); data bit D6
Automatic field detection(AUFD); data bit D7
Switches directly pin 64 GPSW (application dependent);
One Chip Front-end 1 (OCF1)
Controlled by BYPS (subaddress 06) normal position
HS, HREF and VS high impedance/inputs
Field state directly controlled via FSEL
UBADDRESS
UBADDRESS
Disable sync and clamp (set to HIGH)
Digital chrominance input switched to
PLL open, horizontal frequency fixed
second input channel (see Fig.20)
Output HS, HREF and VS active
YUV bus high impedance/input
Automatic field detection
Enable sync and clamp
Output YUV-bus active
50 Hz, 625 lines
60 Hz, 525 lines
0E (
0F (
Reduction on
Reduction off
FUNCTION
FUNCTION
VBLKA = 0
PLL closed
0 steps
3 steps
DATA BYTE
DATA BYTE
4 steps
127 to 120)
119 to 112)
40
YDEL2 = 0; YDEL1 = 0; YDEL0 = 0
YDEL2 = 0; YDEL1 = 1; YDEL0 = 1
YDEL2 = 1; YDEL1 = 0 YDEL1 = 0
CONTROL BITS
CONTROL BITS
GPSW = 0
GPSW = 1
SAA7110; SAA7110A
CHRS = 0
CHRS = 1
OEYC = 0
OEYC = 1
OEHV = 0
OEHV = 1
SCEN = 0
SCEN = 1
SXCR = 0
SXCR = 1
AUFD = 0
AUFD = 1
HPLL = 0
HPLL = 1
FSEL = 0
FSEL = 1
Product specification