saa7110 NXP Semiconductors, saa7110 Datasheet - Page 6

• Manufacturer Part Number: saa7110
• Description: One Chip Front-end 1 Ocf1
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8
1995 Oct 18
SP
AP
RTCO
SA
SDA
SCL
i.c.
i.c.
i.c.
V
AI42
V
AI41
V
AI32
V
AI31
V
AI22
V
AI21
V
AOUT
V
V
LFCO
V
V
LLC
LLC2
CREF
SYMBOL
SSA4
DDA4
SSA3
DDA3
SSA2
DDA2
SS(S)
DDA0
SSA0
DD
SS
One Chip Front-end 1 (OCF1)
PINNING
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9
test pin input; (shift pin) connect to ground for normal operation
test pin input; (action pin) connect to ground for normal operation
Real Time Control Output. This pin is used to fit serially the increments of the HPLL and
FSC-PLL and information of the PAL or SECAM sequence.
I
HIGH = 9DH for write, 9FH for read.
I
I
reserved pin; do not connect
reserved pin; do not connect
reserved pin; do not connect
ground for analog input 4
analog input 42
supply voltage (+5 V) for analog input 4
analog input 41
ground for analog input 3
analog input 32
supply voltage (+5 V) for analog input 3
analog input 31
ground for analog input 2
analog input 22
supply voltage (+5 V) for analog input 2
analog input 21
substrate ground
analog test output; do not connect
supply voltage (+5 V) for internal CGC (Clock Generation Circuit)
ground for internal CGC
Line Frequency Control output; this is the analog clock control signal driving the external
CGC. The frequency is a multiple of the actual line frequency (nominally 7.375/6.13636 MHz).
The signal has a triangular form with 4-bit accuracy.
supply voltage (+5 V)
ground
Line-Locked Clock input/output (CGCE = 1, output; CGCE = 0, input). This is the system
clock, its frequency is 1888
60 Hz/525 lines per field systems; or variable input clock up to 32 MHz in input mode.
Line-Locked Clock
impedance).
Clock reference input/output (CGCE = 1, output; CGCE = 0, input). This is a clock qualifier
signal distributed by the internal or an external clock generator circuit (CGC). Using CREF all
interfaces on the YUV-bus are able to generate a bus timing with identical phase.
2
2
2
C-bus slave address select input. LOW: slave address = 9CH for write, 9DH for read;
C-bus serial data input/output
C-bus serial clock input
1
2
output; f
f
LLC2
h
for 50 Hz/625 lines per field systems and 1560
6
= 0.5
DESCRIPTION
f
LLC
(CGCE = 1, output; CGCE = 0, high
SAA7110; SAA7110A
Product specification
f
h
for