saa7146a NXP Semiconductors, saa7146a Datasheet - Page 42

• Manufacturer Part Number: saa7146a
• Description: Multimedia Bridge, High Performance Scaler And Pci Circuit Spci
• Manufacturer: NXP Semiconductors

Philips Semiconductors
2004 Aug 25
114
OFFSET
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
(HEX)
RPS_RE0
RPS_PE0
RPS_A0
DEBI_TO
DEBI_EF
IIC_EA
IIC_EW
IIC_ER
IIC_EL
IIC_EF
V3P
V2P
V1P
VF3
NAME
26
25
24
23
22
21
20
19
18
17
16
15
14
13
BIT
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TYPE
RPS Task 0 Register access Error: this bit is set when the LDREG,
STREG or MASKWRITE command tries to access a non-existing
register. This bit is reset by writing a logic 1 to the RPS_E0 bit in the ISR
or when a new RPS Task 0 is started.
RPS Task 0 Page Error: this bit is set when the RPS Task 0 tries to
write-access an address outside the 4-kbyte page. This bit is reset by
writing a logic 1 to the RPS_E0 bit in the ISR or when a new RPS Task 0
is started.
RPS Task 0 Active: this bit is set whenever RPS Task 0 is executing
and not staying in a wait condition or uploading the working registers
DEBI Time Out: this bit is set when the TIMEOUT value was reached.
This bit is reset by writing a logic 1 to the DEBI_E bit in the ISR. Reset
value is a logic 1.
DEBI Format Error: this bit indicates an illegal command to immediate
transfer across a Dword boundary. This bit is reset by writing a logic 1 to
the DEBI_E bit in the ISR.
I
after the device address. This bit is reset by writing a logic 1 to the IIC_E
bit in the ISR or when a new I
I
during the writing of the data byte(s). This bit is reset by writing a logic 1
to the IIC_E bit in the ISR or when a new I
I
during reading of the data byte(s). This bit is reset by writing a logic 1 to
the IIC_E bit in the ISR or when a new I
I
arbitration. This bit is reset by writing a logic 1 to the IIC_E bit in the ISR
or when a new I
I
START/STOP condition since the last I
reset by writing a logic 1 to the IIC_E bit in the ISR or when a new
I
Video DMA 3 Protection error: this bit is set when video DMA3
generates an address during an active transmission beyond its
protection address. This bit is reset by writing a logic 1 to the V_PE bit in
the ISR or by reloading the DMA base address.
Video DMA 2 Protection error: this bit is set when video DMA2
generates an address during an active transmission beyond its
protection address. This bit is reset by writing a logic 1 to the V_PE bit in
the ISR or by reloading the DMA base address.
Video DMA 1 Protection error: this bit is set when video DMA1
generates an address during an active transmission beyond its
protection address. This bit is reset by writing a logic 1 to the V_PE bit in
the ISR or by reloading the DMA base address.
Video FIFO 3 underflow/overflow: this bit is set when the video FIFO 3
has an overflow/underflow. This bit is reset when reloading the DMA
base address or by writing a logic 1 to the VFOU bit in the ISR.
2
2
2
2
2
2
C-bus Address Error: this bit is set when there is no acknowledge
C-bus Write data Error: this bit is set when there is no acknowledge
C-bus Read data Error This bit is set when there is no acknowledge
C-bus Loss arbitration Error: this bit is set when the I
C-bus Frame Error: this bit is set when there is an invalid
C-bus command starts.
42
2
C-bus command starts.
DESCRIPTION
2
C-bus command starts.
2
C-bus command. This bit is
2
C-bus command starts.
2
C-bus command starts.
Product specification
SAA7146A
2
C-bus loses its