saa7146a NXP Semiconductors, saa7146a Datasheet - Page 91

• Manufacturer Part Number: saa7146a
• Description: Multimedia Bridge, High Performance Scaler And Pci Circuit Spci
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 89 Clip control
7.13
The RPS is controlled by the PAUSE command on special
events. This section describes the video events. Because
of these video events a defined time for an upload is given.
Table 90 shows the UPLOAD handling for the scaler
registers. For special applications it can also be useful to
select other combinations. For this the termination of the
UPLOAD must guarantee that the UPLOAD is completed
before the processing restarts, e.g. with a new line or a
2004 Aug 25
78H
OFFSET
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Scaler event description
ClipCK
ClipMode
RecInterl
ClipOut
NAME
15 to 10
9 and 8
7
6 to 4
3
2
1 and 0
BIT
RW
RW
RW
RW
TYPE
reserved
clipping by chroma key CK (or MSB of -8): OR-ed with other clip
list or clip-bit mask, if ClipMode is enabled
reserved
clipping based on DMA2 read information: OR-ed with chroma
key CK, if ClipCK is enabled
select interlaced mode for rectangular overlays:
reserved
use of DMA3 to report (write) key of clip information back:
00: chroma key CK is not used for clipping, CK
01: chroma key CK is not used for clipping, inverted CK
10: clipping, based on chroma key CK bit
11: clipping, based on chroma key CK bit inverted
000: no clipping based on DMA2 read, DMA2 can be used to write
decomposed format U
001: no clipping based on DMA2 read, DMA2 reads 8-bit- to
substitute CK in -formats
010: reserved
011: reserved
100: clipping, based on pixel clip list, rectangular overlays
101: clipping, based on pixel clip list, rectangular overlays,
inverted
110: clipping, based on pixel clip bit mask 1-bit/pixel
111: clipping, based on pixel clip bit mask 1-bit/pixel, inverted
0: normal mode
1: interlaced mode, this bit must be set if only one clip list for both
fields is available. This function assumes that the ODD field is
always above the EVEN field.
00: no clip output, DMA3 can be used to write decomposed format
V, or to serve BRS, read or write
01: DMA3 writes chroma key information CK; 1-bit/pixel
10: DMA3 writes back (clip mask-CK); 1-bit /pixel
11: DMA3 writes applied pixel clipping back; 1-bit/pixel
91
new field. To avoid conflicts, e.g. change of vertical
settings during vertical processing, the MASKWRITE
command can be used to change single bits within a
Dword. Each video event can force only one upload at a
time. This means that the video event is cleared by the
circuit as described below, if the corresponding upload has
occurred.
DESCRIPTION
Product specification
SAA7146A