saa7130hl-v1 NXP Semiconductors, saa7130hl-v1 Datasheet - Page 12

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saa7130hl-v1

Manufacturer Part Number
saa7130hl-v1
Description
Pci Video Broadcast Decoder
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
6. Functional description
SAA7130HL_4
Product data sheet
6.1 Overview of internal functions
Table 10:
The SAA7130HL is able to capture TV signals over the PCI-bus in personal computers by
a single chip; see
The SAA7130HL incorporates two 9-bit video ADCs and the entire decoding circuitry for
any analog TV signal: NTSC, PAL and SECAM, including non-standard signals, such as
playback from a VCR. The adaptive multi-line comb filter provides superb picture quality,
component separation, sharpness and high bandwidth. The video stream can be cropped
and scaled to the needs of the application. Scaling down as well as zooming up is
supported in the horizontal and vertical direction, and an adaptive filter algorithm prevents
aliasing artifacts. With the acquisition unit of the scaler two different ‘tasks’ can be defined,
e.g. to capture video to the CPU for compression, and write video to the screen from the
same video source but with different resolution, color format and frame rate.
The SAA7130HL incorporates analog audio pass-through and support for the analog
audio loopback cable to the sound card function.
The decoded video streams are fed to the PCI-bus, and are also applied to a peripheral
streaming interface, in ITU, VIP or VMI format. A possible application extension is
on-board hardware MPEG compression, or other feature processing. The compressed
data is fed back through the peripheral interface, in parallel or serial format, to be captured
by the system memory through the PCI-bus. The Transport Stream (TS) from a DTV/DVB
channel decoder can be captured through the peripheral interface in the same way.
Video and transport streams are collected in a configurable FIFO with a total capacity of
1 kB. The DMA controller monitors the FIFO filling degree and master-writes the audio
and video stream to the associated DMA channel. The virtual memory address space
(from OS) is translated into physical (bus) addresses by the on-chip hardware Memory
Management Unit (MMU).
The application of the SAA7130HL is supported by reference designs and a set of drivers
for the Windows operating system (Windows driver model compliant).
Pin type
PI
PIO
PO
S/T/S
T/S
VG
VS
Name ends with _N or # this pin or ‘signal’ is active LOW, i.e. the function is ‘true’ if the logic level
Characteristics of pin types and remarks
Figure
Rev. 04 — 11 April 2006
Description
input according to PCI-bus requirements
input and output according to PCI-bus requirements
output according to PCI-bus requirements
sustained 3-state (for PCI-bus); previous owner drives HIGH for one
clock cycle before leaving to 3-state
3-state I/O (for PCI-bus); bidirectional
ground for digital supply
supply voltage (3.3 V)
is LOW
4.
…continued
PCI video broadcast decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SAA7130HL
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