ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 10

• Manufacturer Part Number: ep2sgx60e
• Description: 4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
• Manufacturer: Altera Corporation

Active Serial FPGA Configuration
Figure 4–3. Cyclone FPGA Configuration in AS Mode (Serial Configuration Device Programmed by APU or
Third-Party Programmer)
Notes to
(1)
(2)
(3)
(4)
4–10
Configuration Handbook, Volume 2
V
Serial configuration devices cannot be cascaded.
Connect the FPGA MSEL[] input pins to select the AS configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
For more information about configuration pin I/O requirements in an AS scheme for a Cyclone III FPGA, refer to
the
CC
Configuring Cyclone III Devices
Figure
= 3.3 V.
Configuration
Device (2)
Serial
4–3:
DATA
DCLK
ASDI
nCS
Note (4)
10 k
The FPGA acts as the configuration master in the configuration flow and
provides the clock to the serial configuration device. The FPGA enables
the serial configuration device by pulling the nCS signal low via the nCSO
signal (refer to
instructions and addresses to the serial configuration device via the ASDO
signal. The serial configuration device responds to the instructions by
sending the configuration data to the FPGA’s DATA0 pin on the falling
edge of DCLK. The data is latched into the FPGA on the DCLK signal’s
falling edge.
The FPGA controls the nSTATUS and CONF_DONE pins during
configuration in AS mode. If the CONF_DONE signal does not go high at
the end of configuration or if the signal goes high too early, the FPGA will
pulse its nSTATUS pin low to start reconfiguration. Upon successful
configuration, the FPGA releases the CONF_DONE pin, allowing the
external 10-kΩ resistor to pull this signal high. Initialization begins after
the CONF_DONE goes high. After initialization, the FPGA enters user
mode.
V
CC
chapter in volume 1 of the Cyclone III Device Handbook.
(1)
10 k
V
CC
(1) V
Figures 4–2
CC
10 k
(1)
and 4–3). Subsequently, the FPGA sends the
CONF_DONE
nSTATUS
nCONFIG
nCE
DATA0
DCLK
nCSO
ASDO
Cyclone FPGA
MSEL[1..0]
nCEO
Altera Corporation
00
(3)
N.C.
May 2008