ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 27

• Manufacturer Part Number: ep2sgx60e
• Description: 4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
• Manufacturer: Altera Corporation

Figure 4–10. Write Status Operation Timing Diagram
Altera Corporation
May 2008
DCLK
DATA
ASDI
nCS
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
0
High Impedance
1
memory. You must execute the write enable operation before the write
status operation so the device sets the status register’s write enable latch
bit to 1.
The write status operation is implemented by driving nCS low, followed
by shifting in the write status operation code and one data byte for the
status register on the ASDI pin.
the write status operation. nCS must be driven high after the eighth bit of
the data byte has been latched in, otherwise, the write status operation is
not executed.
Immediately after nCS drives high, the device initiates the self-timed
write status cycle. The self-timed write status cycle usually takes 5 ms for
all serial configuration devices and is guaranteed to be less than 15 ms
(refer to t
the status register is written with desired block protect bits. Alternatively,
you can check the write in progress bit in the status register by executing
the read status operation while the self-timed write status cycle is in
progress. The write in progress bit is 1 during the self-timed write status
cycle, and 0 when it is complete.
Read Bytes Operation
The read bytes operation code is b'0000 0011, with the MSB listed first.
To read the memory contents of the serial configuration device, the device
is first selected by driving nCS low. Then, the read bytes operation code
is shifted in followed by a 3-byte address (A[23..0]). Each address bit
must be latched in on the rising edge of the DCLK. After the address is
latched in, the memory contents of the specified address are shifted out
serially on the DATA pin, beginning with the MSB. For reading Raw
Programming Data files (.rpd), the content is shifted out serially
beginning with the LSB. Each data bit is shifted out on the falling edge of
2
Operation Code
3
WS
4
in
5
Table
6
4–23). You must account for this delay to ensure that
7
MSB
7
8
6
Figure 4–10
9
5
10
Status Register
Configuration Handbook, Volume 2
4
11
shows the timing diagram for
3
12
2
13
1
14
0
15
4–27