ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 35
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ep2sgx60e
Manufacturer Part Number
ep2sgx60e
Description
4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP2SGX60E.pdf
(46 pages)
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Timing
Information
Figure 4–17. Write Operation Timing
Altera Corporation
May 2008
f
t
t
t
t
t
t
t
t
t
W C L K
CH
CL
NCSSU
NCSH
DSU
DH
CSH
WB
WS
Table 4–23. Write Operation Parameters (Part 1 of 2)
Symbol
(1)
(1)
DCLK
DATA
ASDI
nCS
t
NCSH
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Write clock frequency (from FPGA, download
cable, or embedded processor) for write enable,
write disable, read status, read silicon ID, write
bytes, erase bulk, and erase sector operations
DCLK
DCLK
Chip select (
Chip select (
Data (
DCLK
Data (
Chip select high time
Write bytes cycle time for EPCS1, EPCS4,
EPCS16, and EPCS64
Write bytes cycle time for EPCS128
Write status cycle time
High Impedance
t
DSU
ASDI
ASDI
high time
low time
) in setup time before rising edge on
) hold time after rising edge on
nCS
nCS
Bit n
Figure 4–17
configuration device.
Table 4–23
write operation.
t
NCSSU
) setup time
) hold time
Parameter
t
DH
defines the serial configuration device timing parameters for
Bit n
shows the timing waveform for write operation to the serial
1
t
CH
DCLK
t
CL
Min
100
Bit 0
20
20
10
10
—
—
—
—
5
5
Configuration Handbook, Volume 2
Typ
1.5
2.5
—
—
—
—
—
—
—
—
5
t
CSH
Max
25
15
—
—
—
—
—
—
—
5
7
MHz
Unit
ms
ms
ms
4–35
ns
ns
ns
ns
ns
ns
ns