ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 32

• Manufacturer Part Number: ep2sgx60e
• Description: 4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
• Manufacturer: Altera Corporation

Serial Configuration Device Memory Access
4–32
Configuration Handbook, Volume 2
You can implement the erase bulk operation by driving nCS low and then
shifting in the erase bulk operation code on the ASDI pin. nCS must be
driven high after the eighth bit of the erase bulk operation code has been
latched in.
The device initiates the self-timed erase bulk cycle immediately after nCS
is driven high. Refer to t
time for the respective EPCS devices.
You must account for this delay before accessing the memory contents.
Alternatively, you can check the write in progress bit in the status register
by executing the read status operation while the self-timed erase cycle is
in progress. The write in progress bit is 1 during the self-timed erase cycle
and 0 when it is complete. The write enable latch bit in the status register
is reset to 0 before the erase cycle is complete.
Figure 4–15. Erase Bulk Operation Timing Diagram
Erase Sector Operation
The erase sector operation code is b'1101 1000, with the MSB listed
first. The erase sector operation allows the user to erase a certain sector in
the serial configuration device by setting all bits inside the sector to 1 or
0xFF. This operation is useful for users who access the unused sectors as
general purpose memory in their applications.
The write enable operation must be executed prior to the erase sector
operation so that the write enable latch bit in the status register is set to 1.
The erase sector operation is implemented by first driving nCS low, then
shifting in the erase sector operation code and the three address bytes of
the chosen sector on the ASDI pin. The three address bytes for the erase
sector operation can be any address inside the specified sector. (Refer to
Tables 4–10
nCS high after the eighth bit of the erase sector operation code has been
latched in.
DCLK
ASDI
nCS
Figure 4–15
Figure 4–16
through
4–14
shows the timing diagram.
shows the timing diagram.
EB
0
for sector address range information.) Drive
in
1
Table 4–23
2
Operation Code
3
for the self-timed erase bulk cycle
4
5
6
7
Altera Corporation
May 2008