DS150 (v1.0) February 2, 2009
General Description
The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Using the third generation ASMBL™ (Advanced
Silicon Modular Block) column-based architecture, the Virtex-6 family contains multiple distinct platforms (sub-families). This overview
covers the devices in the LXT and SXT platforms. Each platform contains a different ratio of features to address the needs of a wide variety
of advanced logic designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built-in system-level blocks,
including 36 Kb block RAM/FIFOs, third generation DSP48E1 slices, SelectIO™ technology with built-in digitally controlled impedance,
ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced mixed-mode clock management blocks,
advanced configuration options, power-optimized high-speed serial transceiver blocks, PCI Express® compatible integrated blocks, and
tri-mode Ethernet media access controllers (MACs). These features allow logic designers to build the highest levels of performance and
functionality into their FPGA-based systems. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 FPGAs are a
programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs.
Virtex-6 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers,
and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.
Summary of Virtex-6 FPGA Features
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© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.
All other trademarks are the property of their respective owners.
DS150 (v1.0) February 2, 2009
Advance Product Specification
Two Base Platforms
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Cross-platform compatibility
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Advanced, high-performance, FPGA Logic
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Powerful mixed-mode clock managers (MMCM) clocking
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36-Kb block RAM/FIFOs
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High-performance parallel SelectIO technology
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Virtex-6 LXT Platform: High-performance logic with
advanced serial connectivity
Virtex-6 SXT Platform: Highest signal processing
capability with advanced serial connectivity
More platforms to follow
LXT and SXT devices are footprint compatible in the
same package
Real 6-input look-up table (LUT) technology
Dual LUT5 (5-LUT) option
LUT/dual flip-flop pair for applications requiring rich
register mix
Improved routing efficiency
64 bit (or 32 x 2 bit) distributed LUT RAM option
SRL32/dual SRL16 with registered outputs option
MMCM blocks provide zero-delay buffering, frequency
synthesis, clock-phase shifting, input-jitter filtering, and
phase-matched clock division
True dual-port RAM blocks
Programmable
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Enhanced programmable FIFO logic
Built-in optional error-correction circuitry
Optionally use each block as two independent 18 Kb
blocks
1.2 to 2.5V I/O operation
Source-synchronous interfacing using
ChipSync™ technology
Digitally controlled impedance (DCI) active termination
Flexible fine-grained I/O banking
High-speed memory interface support with integrated
write-leveling capability
True dual-port widths up to 36 bits
Simple dual-port widths up to 72 bits
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Advanced DSP48E1 slices
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Flexible configuration options
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System Monitor capability on all devices
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Integrated interface blocks for PCI Express designs
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RocketIO™ GTX transceivers 150 Mb/s to 6.5 Gb/s
Integrated 10/100/1000 Mb/s Ethernet MAC block
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40 nm copper CMOS process technology
1.0V core voltage (-1, -2, -3 speed grades only)
Lower-power 0.9V core voltage (-1L speed grade only)
High signal-integrity flip-chip packaging available in standard
or Pb-free package options
25 x 18, two's complement multiplier/accumulator
Optional pipelining
New optional pre-adder to assist filtering applications
Optional bitwise logic functionality
Dedicated cascade connections
SPI and Parallel Flash interface
Multi-bitstream support with dedicated fallback
reconfiguration logic
Automatic bus width detection
On-chip/off-chip thermal and supply voltage monitoring
JTAG access to all monitored quantities
Designed to the PCI Express Base Specification 2.0
Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with GTX
transceivers
Endpoint and Root Port capable
x1, x2, x4, or x8 lane support per block
One virtual channel, eight traffic classes
Supported 1000BASE-X PCS/PMA and SGMII using
RocketIO GTX transceivers
Supports MII, GMII, and RGMII using SelectIO
resources
2500Mb/s support available
Virtex-6 Family Overview
Advance Product Specification
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