at94k05al-25aqi ATMEL Corporation, at94k05al-25aqi Datasheet - Page 53

• Manufacturer Part Number: at94k05al-25aqi
• Description: 5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
• Manufacturer: ATMEL Corporation

FPGA Cache Logic
FPGA I/O
Selection by AVR
Rev. 1138F–FPSLI–06/02
FPGA Cache Data Register – FPGAD
The FPGAD I/O Register address is not supported by a physical register; it is simply the I/O
address that, if written to, generates the FPGA Cache I/O write strobe. The CACHEIOWE sig-
nal is a qualified version of the AVR IOWE signal. It will only be active if an OUT or ST (store
to) instruction references the FPGAD I/O address. The FPGAD I/O address is write-sensitive-
only; an I/O read to this location is ignored. If the AVR Cache Interface bit in the SCR [BIT62]
is set (one), the data being “written” to this address is cached to the FPGA address specified
by the FPGAX..Z registers (see below) during the active CACHEIOWE strobe.
FPGA Cache Z Address Registers – FPGAX..Z
The three FPGA Cache address registers combine to form the 24-bit address, CAC-
HEADDR[23:0], delivered to the FPGA cache logic outside the AVR block during a write to the
FPGAD I/O Register (see above).
Sixteen select signals are sent to the FPGA for I/O addressing. These signals are decoded
from four I/O registry addresses (FISUA...D) and extended to sixteen with two bits from the
FPGA I/O Select Control Register (FISCR). In addition, the FPGAIORE and FPGAIOWE sig-
nals are qualified versions of the IORE and IOWE signals. Each will only be active if one of the
four base I/O addresses are referenced. It is necessary for the FPGA design to implement any
required registers for each select line; each qualified with either the FPGAIORE or
FPGAIOWE strobe. Refer to the FPGA/AVR Interface section for more details. Only the
FISCR registers physically exist. The FISUA...D I/O addresses for the purpose of FPGA I/O
selection are NOT supported by AVR Core I/O space registers; they are simply I/O addresses
(available to 1 cycle IN/OUT instructions) which trigger appropriate enabling of the FPGA
select lines and the FPGA IORE/IOWE strobes (see Figure 18 on page 21).
FPGA I/O Select Control Register – FISCR
• Bit 7 - FIADR: FPGA Interrupt Addressing Enable
When FIADR is set (one), the four dual-purpose I/O addresses, FISUA..D, are mapped to four
physical registers that provide memory space for FPGA interrupt masking and interrupt flag
status. When FIADR is cleared (zero), and I/O read or write to one of the four dual-purpose I/O
addresses, FISUA..D, will access its associated group of four FPGA I/O select lines. The
XFIS1 and XFIS0 bits (see Table 12) further determine which one select line in the accessed
group is set (one). A read will assign the FPGA I/O read enable to the AVR I/O read enable
(FPGAIORE
Bit
$1B ($3B)
Read/Write
Initial Value
Bit
$18 ($38)
$19 ($39)
$1A ($3A)
Read/Write
Initial Value
Bit
$13 ($33)
Read/Write
Initial Value
←
7
FIADR
R/W
0
7
MSB
W
N/A
7
FCX7
FCY7
FCT3
R/W
0
IORE) and a write, the FPGA I/O write enable to the AVR I/O write enable
6
W
N/A
6
FCX6
FCY6
FCT2
R/W
0
6
-
R
0
5
W
N/A
5
FCX5
FCY5
FCT1
R/W
0
5
-
R
0
4
W
N/A
4
-
R
0
4
FCX4
FCY4
FCT0
R/W
0
3
W
N/A
3
FCX3
FCY3
FCZ3
R/W
0
3
-
R
0
AT94K Series FPSLIC
2
W
N/A
2
-
R
0
2
FCX2
FCY2
FCZ2
R/W
0
1
W
N/A
1
XFIS1
R/W
0
1
FCX1
FCY1
FCZ1
R/W
0
0
LSB
W
N/A
0
XFIS0
R/W
0
0
FCX0
FCY0
FCZ0
R/W
0
FPGAD
FISCR
FPGAX
FPGAY
FPGAZ
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