at94k05al-25aqi ATMEL Corporation, at94k05al-25aqi Datasheet - Page 80

• Manufacturer Part Number: at94k05al-25aqi
• Description: 5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
• Manufacturer: ATMEL Corporation

Scanning 2-wire Serial
Scanning the Clock Pins
80
AT94K Series FPSLIC
The SCL and SDA pins are open drain, bi-directional and enabled separately. The “Enable
Output” bits (active High) in the scan chain are supported by general boundary-scan cells.
Enabling the output will drive the pin Low from a tri-state. External pull-ups on the 2-wire bus
are required to pull the pins High if the output is disabled. The “Data Out/In” and “Clock Out/In”
bits in the scan chain are observe-only cells. Figure 46 shows how each pin is connected in
the scan chain.
Figure 46. Boundary-scan Cells for 2-wire Serial
Figure 47 shows how each oscillator with external connection is supported in the scan chain.
The Enable signal is supported with a general boundary-scan cell, while the oscillator/clock
output is attached to an observe-only cell. In addition to the main clock, the timer oscillator is
scanned in the same way. The output from the internal RC-Oscillator is not scanned, as this
oscillator does not have external connections.
Figure 47. Boundary-scan Cells for Oscillators and Clock Options
From digital logic
To 2-wire
Serial Logic
From 2-wire
Serial Logic
previous
From
cell
ShiftDR
0
1
ClockDR UpdateDR
D Q
next
cell
Data or Clock Out/In
(Observe Only Cell)
To
From Previous Cell
To Next Cell
Enable Output
(General Boundary
Scan Cell)
D Q
G
EXTEST
0
1
XTAL1/TOSC1
ENABLE
Oscillator
XTAL2/TOSC2
OUTPUT
previous
From
cell
ShiftDR
0
1
ClockDR
D Q
FF1
Rev. 1138F–FPSLI–06/02
next
cell
To
SDA or
SCL
To system logic