at94k05al-25aqi ATMEL Corporation, at94k05al-25aqi Datasheet - Page 55

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at94k05al-25aqi

Manufacturer Part Number
at94k05al-25aqi
Description
5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
Manufacturer
ATMEL Corporation
Datasheet

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General AVR/FPGA I/O
Select Procedure
Rev. 1138F–FPSLI–06/02
I/O select depends on the FISCR register setup and the FISUA..D register written to or read
from.
The following FISCR setups and writing data to the FISUA..D registers will result in the shown
I/O select lines and data presented on the 8-bit AVR–FPGA data bus.
Table 13. FISCR Register Setups and I/O Select Lines.
Note:
FIADR(b7)
;---------------------------------------------
io_select0_write:
;---------------------------------------------
io_select13_read:
0
0
0
0
ldi r16,0x00
out FISCR,r16
out FISUA,r17;
ret
ldi r16,0x01
out FISCR,r16
in r18,FISUD
ret
1. IOSEL 15..8 are not available on AT94K05.
FISCR Register
b6-2
-
-
-
-
XFIS1(b1)
0
0
1
1
;FIADR=0,XFIS1=0,XFIS0=0 ->I/O select line=0
;load I/O select values into FISCR register
;select line 0 high. Place data on AVR<->FPGA bus
; from r17 register. (out going data is assumed
; to be present in r17 before calling this subroutine)
;FIADR=0,XFIS1=0,XFIS0=1 ->I/O select line=13
;load I/O select values into FISCR register
;select line 13 high. Read data on AVR<->FPGA bus
;which was placed into register FISUD.
XFIS0(b0)
0
1
0
1
IOSEL 0
IOSEL 1
IOSEL 2
IOSEL 3
FISUA
AT94K Series FPSLIC
IOSEL 4
IOSEL 5
IOSEL 6
IOSEL 7
FISUB
I/O Select Lines
IOSEL 10
IOSEL 11
IOSEL 8
IOSEL 9
FISUC
(1)
IOSEL 12
IOSEL 13
IOSEL 14
IOSEL 15
FISUD
55

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