cy8c20436an-24lqxit Cypress Semiconductor Corporation., cy8c20436an-24lqxit Datasheet - Page 18

• Manufacturer Part Number: cy8c20436an-24lqxit
• Description: Capsense Applications
• Manufacturer: Cypress Semiconductor Corporation.

DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 13. DC Chip-Level Specifications
1. When V
3. For USB mode, the V
4. For proper CapSense block functionality, if the drop in V
Document Number: 001-54459 Rev. *D
V
I
I
I
I
I
2. If powering down in standby sleep mode, to properly detect and recover from a V
DD24
DD12
DD6
SB0
SB1
DD
a. Bring the device out of sleep before powering down.
b. Assure that V
c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d. Increase the buzz rate to assure that the falling edge of V
Symbol
slower than 1V/500 usec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SR
be between 1.8 V and 5.5 V..
[1, 2, 3, 4]
For the referenced registers, refer to the CY8C20x36 Technical Reference Manual . In deep sleep mode, additional low power voltage monitoring circuitry allows V
brown out conditions to be detected for edge rates slower than 1V/ms.
DD
remains in the range from 1.71V to 1.9V for more than 50 µsec, the slew rate when moving from the 1.71V to 1.9V range to greater than 2V must be
Supply Voltage
Supply Current, IMO = 24 MHz
Supply Current, IMO = 12 MHz
Supply Current, IMO = 6 MHz
Deep Sleep Current
Standby Current with POR, LVD and
Sleep Timer
DD
falls below 100 mV before powering back up.
DD
supply for bus-powered application should be limited to 4.35V-5.35V. For self-powered application, V
Description
DD
DD
exceeds 5% of the base V
Refer the table
Specifications on page 23
Conditions are V
CPU = 24 MHz. CapSense running at 12
MHz, no I/O sourcing current
Conditions are V
CPU = 12 MHz. CapSense running at
12 MHz, no I/O sourcing current
Conditions are V
CPU = 6 MHz. CapSense running at 6 MHz,
no I/O sourcing current
V
V
is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.
DD
DD
 3.0 V, T
 3.0 V, T
A
A
= 25 C, I/O regulator turned off
= 25 C, I/O regulator turned off
DC POR and LVD
DD
Conditions
DD
DD
DD
brown out condition any of the following actions must be taken:
DD
 3.0 V, T
 3.0 V, T
 3.0 V, T
, the rate at which V
A
A
A
= 25 C,
= 25 C,
= 25 C,
CY8C20X36A/46A/66A/96A
DD
drops should not exceed 200 mV/s. Base V
1.71
Min
DD
–
–
–
–
–
should be 3.15V-3.45V.
3.32
1.86
1.13
0.10
1.07
Typ
–
POWER_UP
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Max
5.50
4.00
2.60
1.80
0.50
1.50
[+] Feedback
parameter.
Units
DD
mA
mA
mA
A
A
V
can
DD