mm908e626 Freescale Semiconductor, Inc, mm908e626 Datasheet - Page 20

• Manufacturer Part Number: mm908e626
• Description: Integrated Stepper Motor Driver With Embedded Mcu And Lin Serial Communication
• Manufacturer: Freescale Semiconductor, Inc

prepared. The falling edge on the
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of
the register by the rising edge of
internally latched into the SPI at the time when the parity bit
is transferred.
MASTER ADDRESS BYTE
A4 : A0
R /
20
908E626
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPSCK
W
MOSI
MISO
During the inactive phase of
The MISO output changes data on a rising edge of
After a write operation, the transmitted data is latched into
Contains the address of the desired register.
Contains information about a read or a write operation.
SS
Rising edge of SPSCK
Change MISO/MOSI
SS
HIGH forces MISO to high impedance.
Output
R/W
S7
Falling edge of SPSCK
Sample MISO/MOSI
Input
A4
S6
SS
SS
SS
, the new data transfer is
Read/Write, Address, Parity
A3
S5
. Register read data is
System Status Register
line indicates the start
A2
S4
A1
S3
SS
.
A0
S2
Figure 10. SPI Protocol
Slave latch
register address
S1
P
S0
X
Parity P
even number contained within R/
1 bits is odd, P equals “1”. For example, if R/
00001, then P equals “0.”
Bit X
Master Data Byte
Table 2. Contains data to be written or no valid data during
• If R/
• If R/
The parity bit is equal to “0” if the number of 1 bits is an
The parity bit is only evaluated during a write operation.
Not used.
information, slave just transmits back register data.
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the SMARTMOS register on rising edge of
SS
.
W
W
a read operation.
= 1, the second byte of master contains no valid
= 0, the master sends data to be written in the
D7
D7
D6
D6
D5
D5
Analog Integrated Circuit Device Data
Data (Register write)
Data (Register read)
D4
D4
D3
D3
W
Freescale Semiconductor
, A4 : A0. If the number of
D2
D2
D1
D1
W
D0
D0
Slave latch
= 1, A4 : A0 =
data