ksz8893mqlam Micrel Semiconductor, ksz8893mqlam Datasheet - Page 22

• Manufacturer Part Number: ksz8893mqlam
• Description: Integrated 3-port 10/100 Managed Switch With Phys
• Manufacturer: Micrel Semiconductor

December 2007
Ball Number
A1
B1
C3
C1
C2
D1
D2
F2
F1
G2
G1
H2
H1
J1
K1
J2
K2
J3
K3
J4
K4
J5
K5
K6
J6
J7
Ball Name
P1FFC
PWRDN
FXSD1
RXP1
RXM1
TXP1
TXM1
RXM2
RXP2
TXM2
TXP2
ISET
X1
X2
RST_N
LEDSEL0
SMTXEN
SMTXD3
SMTXD2
SMTXD1
SMTXD0
SMTXER
SMTXC /
REFCLK
SMRXC
SMRXDV
SMRXD3
Type
Ipd
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
I
I
I/O
I/O
O
Ipd/O
Ipu
O
Ipu
I
I
(1)
Ball Function Description
1 = always enable (force) port 1 flow control feature
0 = port 1 flow control feature enable is determined by auto
negotiation result.
Chip power down input (active low)
Fiber signal detect / factory test pin
Physical receive or transmit signal (+ differential)
Physical receive or transmit signal (– differential)
Physical transmit or receive signal (+ differential)
Physical transmit or receive signal (– differential)
Physical receive or transmit signal (– differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (– differential)
Physical transmit or receive signal (+ differential)
Set physical transmit output current.
Pull-down this pin with a 3.01K 1% resistor to ground.
25MHz crystal/oscillator clock connections
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1
connects to a 3.3V tolerant oscillator and X2 is a no connect.
Note: Clock is +/- 50ppm for both crystal and oscillator.
Hardware reset pin (active low)
LED display mode select
See description in pins 1 and 4.
Switch MII transmit enable
Switch MII transmit data bit 3
Switch MII transmit data bit 2
Switch MII transmit data bit 1
Switch MII transmit data bit 0
Switch MII transmit error
Switch MII transmit clock (MII and SNI modes only)
Reference Clock (RMII mode only)
Note: In RMII mode, pin X1 is pulled up to VDDIO supply with
a 10K resistor and pin X2 is a no connect.
Switch MII receive clock.
Switch MII receive data valid
Switch MII receive data bit 3
Strap option: switch MII full-duplex flow control
22
Output in PHY MII mode and SNI mode
Input in MAC MII mode
Input for 50MHz +/- 50ppm system clock
Output in PHY MII mode
Input in MAC MII mode
PD (default) = disable
PU = enable
M9999-121007-1.5