ksz8893mqlam Micrel Semiconductor, ksz8893mqlam Datasheet - Page 97

• Manufacturer Part Number: ksz8893mqlam
• Description: Integrated 3-port 10/100 Managed Switch With Phys
• Manufacturer: Micrel Semiconductor

“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these
counters are shown in the following table:
Offset
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
December 2007
Bit
30-16
15-0
Examples:
1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)
Counter Name
Rx1024to1522Octets
TxLoPriorityByte
TxHiPriorityByte
TxLateCollision
TxPausePkts
TxBroadcastPkts
TxMulticastPkts
TxUnicastPkts
TxDeferred
TxTotalCollision
TxExcessiveCollision
TxSingleCollision
TxMultipleCollision
Then
Offset
0x100
0x101
0x102
0x103
0x104
0x105
Write to reg. 121 (0x79) with 0x1c
Write to reg. 122 (0x7A) with 0x0e
Name
Reserved
Counter Value
Table 22. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets
Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets
Counter Name
Port1 TX Drop Packets
Port2 TX Drop Packets
Port3 TX Drop Packets
Port1 RX Drop Packets
Port2 RX Drop Packets
Port3 RX Drop Packets
Table 21. Format of “All Port Dropped Packet” MIB Counters
Description
Total Rx packets (bad packets included) that are between 1024 and 1522 octets in
length (upper limit depends on max packet size setting)
Tx lo-priority good octet count, including PAUSE packets
Tx hi-priority good octet count, including PAUSE packets
The number of times a collision is detected later than 512 bit-times into the Tx of a
packet
Number of PAUSE frames transmitted by a port
Tx good broadcast packets (not including error broadcast or valid multicast packets)
Tx good multicast packets (not including error multicast packets or valid broadcast
packets)
Tx good unicast packets
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium
Tx total collision, half duplex only
A count of frames for which Tx fails due to excessive collisions
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
Successfully Tx frames on a port for which Tx is inhibited by more than one collision
R/W
N/A
RO
Reserved
Description
Counter Value
Description
TX packets dropped due to lack of resources
TX packets dropped due to lack of resources
TX packets dropped due to lack of resources
RX packets dropped due to lack of resources
RX packets dropped due to lack of resources
RX packets dropped due to lack of resources
97
// Read MIB counters selected
// Trigger the read operation
Default
N/A
0
M9999-121007-1.5