ksz8893mqlam Micrel Semiconductor, ksz8893mqlam Datasheet - Page 50

• Manufacturer Part Number: ksz8893mqlam
• Description: Integrated 3-port 10/100 Managed Switch With Phys
• Manufacturer: Micrel Semiconductor

This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in
applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8893MQL/MBL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8893MQL/MBL is typically programmed using an EEPROM. If no EEPROM is
present, the KSZ8893MQL/MBL is configured using its default register settings. Some default settings are
configured via strap-in pin options. The strap-in pins are indicated in the “KSZ8893MQL/MBL Pin Description and
I/O Assignment” table.
I
With an additional I
like “broadcast storm protection” and “rate control” without the need of an external processor.
For KSZ8893MQL/MBL I
register 120 (as defined in the KSZ8893MQL/MBL register map) with the exception of the “Read Only” status
registers. After the de-assertion of reset, the KSZ8893MQL/MBL sequentially reads in the configuration data for
all 121 registers, starting from register 0. The configuration access time (t
the following figure.
The following is a sample procedure for programming the KSZ8893MQL/MBL with a pre-configured EEPROM:
1. Connect the KSZ8893MQL/MBL to the EEPROM by joining the SCL and SDA signals of the respective
2. Enable I
3. Check to ensure that the KSZ8893MQL/MBL reset signal input, RST_N (pin 67), is properly connected to the
4. Program the desired configuration data into the EEPROM.
5. Place the EEPROM on the board and power up the board.
6. Assert an active-low reset to the RST_N pin of the KSZ8893MQL/MBL. After reset is de-asserted, the
Note: For proper operation, check to ensure that the KSZ8893MQL/MBL PWRDN input signal (pin 36) is not
asserted during the reset operation. The PWRDN input is active low.
2
December 2007
C Master Serial Bus Configuration
devices. For the KSZ8893MQL/MBL, SCL is pin 97 and SDA is pin 98.
respectively) to “00”.
external reset source at the board level.
KSZ8893MQL/MBL begins reading the configuration data from the EEPROM. The KSZ8893MQL/MBL checks
that the first byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration continues. If
not, EEPROM configuration access is denied and all other data sent from the EEPROM is ignored by the
KSZ8893MQL/MBL. The configuration access time (t
RST_N
SCL
SDA
2
C master mode by setting the KSZ8893MQL/MBL strap-in pins, PS[1:0] (pins 100 and 101,
2
C (“2-wire”) EEPROM, the KSZ8893MQL/MBL can perform more advanced switch features
Figure 7. KSZ8893MQL/MBL EEPROM Configuration Timing Diagram
2
C Master configuration, the EEPROM stores the configuration data for register 0 to
50
prgm
) is less than 15ms.
t
prgm
prgm
....
....
....
<15 ms
) is less than 15 ms, as depicted in
M9999-121007-1.5