z80180 ZiLOG Semiconductor, z80180 Datasheet - Page 47

• Manufacturer Part Number: z80180
• Description: Microprocessor Unit
• Manufacturer: ZiLOG Semiconductor

ASCI Receive Register Channel 1R
ASCI Channel Control Register A
ASCI Channel Control Register A
PS014004-1106
Bit
Bit
Channel 1
Mnemonics TSR1 (Address (09h)
MPE: Multi-Processor Mode Enable (bit 7)—
multiprocessor communication mode that utilizes an extra data bit for selective
communication when a number of processors share a common serial bus. Multiprocessor
data format is selected when the
selected (
MPE
If
the
MPE
MPE
R/W
R/W
MBE
7
7
RDRF
enables or disables the wake-up feature as follows.
is set to
MP
ASCI Control Register A 0 (CNTLA0: I/O Address = 00h)
ASCI Control Register A 1 (CNTLA1: I/O Address = 01h)
and error flags. Effectively, other bytes (with
R/W
R/W
RE
RE
6
6
Figure 31. ASCI Receive Register Channel 1R
bit in
Figure 32. ASCI Channel Control Register A
1
, only received bytes in which the
7
—
CNTLB = 0
R/W
R/W
TE
TE
5
5
6
—
RTS0
5
—
R/W
R/W
__
4
4
),
MPE
MP
—
—
4
bit in
MPBR/
EFR
MPBR/
EFR
exhibits no effect. If multiprocessor mode is selected,
R/W
R/W
—
3
3
3
ASCI Receive Data
CNTLB
2
—
MOD2
MOD2
R/W
R/W
The ASCI features a
2
2
—
1
is set to
MPB
MPB = 0
MOD1
MOD1
R/W
R/W
(multiprocessor bit) =
1
1
1
. If multiprocessor mode is not
) are ignored by the
MOD0
MOD0
R/W
R/W
0
0
Microprocessor Unit
1
Architecture
can affect
ASCI
Z80180
. If
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