z80180 ZiLOG Semiconductor, z80180 Datasheet - Page 6
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z80180
Manufacturer Part Number
z80180
Description
Microprocessor Unit
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z80180.pdf
(85 pages)
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PS014004-1106
DMA Source Address Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DMA Destination Address Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Byte Count Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DMA Memory Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DMA I/O Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DMA/WAIT Control Register (DCNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt Vector Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
MMU Common Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MMU Bank Base Register (BBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MMU Common/Bank Area Register (CBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Operation Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DMA Source Address Register, Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . 54
DMA Source Address Register, Channel 0H . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Source Address Register Channel 0B . . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Destination Address Register Channel 0L . . . . . . . . . . . . . . . . . . . . . 56
DMA Destination Address Register Channel 0H . . . . . . . . . . . . . . . . . . . . . 56
DMA Destination Address Register Channel 0B . . . . . . . . . . . . . . . . . . . . . 56
DMA Byte Count Register Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DMA Byte Count Register Channel 0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DMA Byte Count Register Channel 1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DMA Byte Count Register Channel 1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DMA Memory Address Register, Channel 1L . . . . . . . . . . . . . . . . . . . . . . . 59
DMA Memory Address Register, Channel 1H . . . . . . . . . . . . . . . . . . . . . . . 60
DMA Memory Address Register, Channel 1B . . . . . . . . . . . . . . . . . . . . . . . 60
DMA I/O Address Register Channel 1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DMA I/O Address Register Channel 1H . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DMA I/O Address Register Channel 1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DMA Status Register (DSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DMA Mode Register (DMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Microprocessor Unit
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