z80180 ZiLOG Semiconductor, z80180 Datasheet - Page 49

• Manufacturer Part Number: z80180
• Description: Microprocessor Unit
• Manufacturer: ZiLOG Semiconductor

ASCI Channel Control Register B
ASCI Channel Control Register B
PS014004-1106
Bit
MPBT
R/W
7
Table 11. Data Formats
MPBT: Multiprocessor Bit Transmit (bit 7)—
is selected (
= 1
undefined during and after
MP: Multiprocessor Mode (bit 6)—
multiprocessor mode based on the
bits) bits in
Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits
Multiprocessor (
If
bit is cleared to
CTS/PS: Clear to Send/Prescale (bit 5)—If bit
is
MOD2
0
0
0
0
1
1
1
1
MP = 0
0
, then
, the
ASCI Control Register B 0 (CNTLB0: I/O Address = 02h)
ASCI Control Register B 1 (CNTLB1: I/O Address = 03h)
R/W
MP
CTS0
6
, the data format is based on
MPB = 1
MOD1
0
0
1
1
0
0
1
1
MP
CNTLA
/
RxS
Figure 33. ASCI Channel Control Register B
bit =
0
CTS/
PS
R/W
MP=1
during
5
is transmitted. If
MOD0
0
1
0
1
0
1
0
1
pin features the
. The format is as follows.
1
) format does not feature any provision for parity.
),
MPBT
RESET
PEO
R/W
4
RESET
Data Format
Start + 7 bit data + 1 stop
Start + 7 bit data + 2 stop
Start + 7 bit data + parity + 1 stop
Start + 7 bit data + parity + 2 stop
Start + 8 bit data + 1 stop
Start + 8 bit data + 2 stop
Start + 8 bit data + parity + 1 stop
Start + 8 bit data + parity + 2 stop
is used to specify the
.
.
CTS0
R/W
MOD2
MPBT = 0
DR
3
When
MOD0
function, and the state of the pin can be read in bit
(number of data bits) and
MP
,
SS2
R/W
MOD1
, then
2
When multiprocessor communication format
is set to
MPB = 0
,
MPB
MOD2
5
R/W
SS1
1
of the System Configuration Register
1
, the data format is configured for
data bit for transmission. If
, and may include parity. The
is transmitted.
SS0
R/W
0
MOD0
Microprocessor Unit
(number of stop
MPBT
Architecture
state is
Z80180
MPBT
MP
5
43