mc68hc908qb4 Freescale Semiconductor, Inc, mc68hc908qb4 Datasheet - Page 143

• Manufacturer Part Number: mc68hc908qb4
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

14.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
At power on, the following events occur:
See
14.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least
every (2
possible out of reset to guarantee the maximum amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break
auxiliary register (BRKAR).
14.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
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Figure
ADDRESS BUS
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive BUSCLKX4.
Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
The POR bit of the SIM reset status register (SRSR) is set.
BUSCLKX4
BUSCLKX2
12
PORRST
– 2
OSC1
14-6.
RST
4
) BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as
CYCLES
4096
MC68HC908QB8 Data Sheet, Rev. 2
Figure 14-6. POR Recovery
(RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR)
CYCLES
32
CYCLES
32
$FFFE
Reset and System Initialization
$FFFF
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