mc68hc908qz16 Freescale Semiconductor, Inc, mc68hc908qz16 Datasheet - Page 146

• Manufacturer Part Number: mc68hc908qz16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MSCAN08 Controller (MSCAN08)
12.13.5 MSCAN08 Receiver Flag Register (CRFLG)
All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding
bit position. A flag can be cleared only when the condition which caused the setting is valid no more.
Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the
CRIER register. A hard or soft reset will clear the register.
WUPIF — Wakeup Interrupt Flag
RWRNIF — Receiver Warning Interrupt Flag
1. Condition to set the flag: RWRNIF = (96 → REC) & RERRIF & TERRIF & BOFFIF
146
TSEG13
1. This setting is not valid. Please refer to
If the MSCAN08 detects bus activity while in sleep mode, it sets the WUPIF flag. If not masked, a
wakeup interrupt is pending while this flag is set.
This flag is set when the MSCAN08 goes into warning status due to the receive error counter (REC)
exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set
masked, an error interrupt is pending while this flag is set.
0
0
0
0
1
.
.
1 = MSCAN08 has detected activity on the bus and requested wakeup.
0 = No wakeup interrupt has occurred.
1 = MSCAN08 has gone into receiver warning status.
0 = No receiver warning status has been reached.
TSEG12
0
0
0
0
1
.
.
Address:
Reset:
Read:
Write:
TSEG11
WUPIF
$0504
0
0
1
1
1
Bit 7
.
.
0
Figure 12-20. Receiver Flag Register (CRFLG)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
TSEG10
RWRNIF
0
1
0
1
1
.
.
6
0
Table 12-8. Time Segment Values
Table 12-4
TWRNIF
2 T
3T
16 T
1 T
Segment 1
4 T
5
0
q
q
q
Time
q
Cycles
for valid settings.
Cycles
q
Cycle
Cycles
.
.
Cycles
RERRIF
(1)
(1)
(1)
4
0
TERRIF
3
0
TSEG22
0
0
1
.
.
BOFFIF
2
0
TSEG21
0
0
1
.
.
OVRIF
1
0
TSEG20
Freescale Semiconductor
0
1
1
.
.
Bit 0
RXF
0
1 T
2 T
Segment 2
8T
(1)
q
q
Time
q
. If not
Cycle
Cycles
Cycles
.
.
(1)