mc68hc908qz16 Freescale Semiconductor, Inc, mc68hc908qz16 Datasheet - Page 238

• Manufacturer Part Number: mc68hc908qz16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI) Module
The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve
power, it is enabled only when both the SPE and SPMSTR bits are set. SPSCK edges occur halfway
through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where
the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the
initiation delay shown in
maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for
DIV32, and 128 MCU bus cycles for DIV128.
238
SPSCK CYCLE
CPHA = 1
CPHA = 0
NUMBER
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
SPSCK
SPSCK
MOSI
BUS
BUS
BUS
BUS
BUS
Figure
Figure 17-8. Transmission Start Delay (Master)
TO SPDR
TO SPDR
TO SPDR
WRITE
WRITE
WRITE
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
TO SPDR
TO SPDR
WRITE
WRITE
17-8. This delay is no longer than a single SPI bit time. That is, the
EARLIEST
EARLIEST
EARLIEST
EARLIEST
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
LATEST
SPSCK = INTERNAL CLOCK ÷ 128;
SPSCK = INTERNAL CLOCK ÷ 32;
SPSCK = INTERNAL CLOCK ÷ 8;
INITIATION DELAY
128 POSSIBLE START POINTS
32 POSSIBLE START POINTS
8 POSSIBLE START POINTS
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
MSB
1
BIT 6
2
LATEST
LATEST
LATEST
BIT 5
3
Freescale Semiconductor