mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 212

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mc68hc908gr8b

Manufacturer Part Number
mc68hc908gr8b
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Timer Interface Module (TIM1 and TIM2)
17.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
See
212
Figure 17-13
Address: T1CH0H, $0026 and T2CH0H, $0031
Address: T1CH0L, $0027 and T2CH0L $0032
Address: T1CH1H, $0029
Address: T1CH1L, $002A
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
through
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Figure 17-13. TIM Channel 0 Register High (TCH0H)
Figure 17-15. TIM Channel 1 Register High (TCH1H)
Figure 17-14. TIM Channel 0 Register Low (TCH0L)
Figure 17-16. TIM Channel 1 Register Low (TCH1L)
Figure
14
14
17-16.
6
6
6
6
6
6
MC68HC908GR8B Data Sheet, Rev. 3.0
0:0), writing to the high byte of the TIM channel x registers
13
13
5
5
5
5
5
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
12
12
4
4
4
4
4
4
11
11
3
3
3
3
3
3
10
10
2
2
2
2
2
2
1
9
1
1
1
9
1
1
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0

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