mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 232

• Manufacturer Part Number: mc68hc908gr8b
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Electrical Specifications
232
10. Pullups and pulldowns are disabled. Port B leakage is specified in
11. Digital inputs have hysteresis whenever they are configured for any alternative peripheral input function other than as a
12. Maximum is highest voltage that POR is possible.
13. If minimum V
Low-voltage inhibit, trip falling voltage – target
Low-voltage inhibit, trip rising voltage – target
Low-voltage inhibit reset/recover hysteresis – target
Input hysteresis (alternative input functions only)
POR reset voltage
POR rise time ramp rate
6. This parameter is characterized and not tested on each device.
7. All functional non-supply pins are internally clamped to V
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 C only.
3. Run (operating) I
4. Wait I
5. Stop I
8. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calcu-
9. Power supply must maintain regulation within operating V
(V
loads. Less than 100 pF on all outputs. C
affects run I
than 100 pF on all outputs. C
I
No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
late resistance values for positive and negative clamp voltages, then use the larger of the two values.
conditions. If positive injection current (V
result in external power supply going out of regulation. Ensure external V
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
general-purpose input.
V
DD
TRIPF
DD
DD
. Measured with PLL and LVI enabled.
is reached.
= 5.0 Vdc
DD
DD
+ V
measured using external square wave clock source (f
with TBM enabled is measured using an external crystal clock source (f
HYS
DD
DD
. Measured with all modules enabled.
= V
(12)
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
DD
10%, V
Characteristic
TRIPR
measured using external square wave clock source (f
(13)
)
SS
= 0 Vdc, T
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
(1)
A
MC68HC908GR8B Data Sheet, Rev. 3.0
= T
IN
L
> V
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
L
(6), (11)
to T
DD
) is greater than I
H
, unless otherwise noted
SS
DD
V
and V
Symbol
V
V
V
range during instantaneous and operating maximum current
PORRST
R
V
osc
TRIPR
TRIPF
InHYS
HYS
POR
= 32.8 MHz). All inputs 0.2 V from rail. No dc loads. Less
DD
DD
19.12 ADC
.
, the injection current may flow out of V
DD
0.06 x V
osc
load will shunt current greater than maximum
0.035
2.35
2.45
= 32.8 MHz). All inputs 0.2 V from rail. No dc
Min
—
0
Characteristics.
OSC
DD
= 8 MHz). All inputs 0.2 V from rail.
Typ
2.60
2.66
700
60
—
—
(2)
Freescale Semiconductor
Max
2.70
2.80
800
—
—
—
DD
and could
V/ms
Unit
mV
mV
V
V
V